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| Freescale Semiconductor, Inc. HC05CT4GRS/D REV. 2.0 Freescale Semiconductor, Inc... General Release Specification For More Information On This Product, Go to: www.freescale.com NON-DISCLOSURE September 15, 1997 AGREEMENT 68HC05CT4 REQUIRED Freescale Semiconductor, Inc. General Release Specification REQUIRED NON-DISCLOSURE General Release Specification For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . 15 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Freescale Semiconductor, Inc... Section 3. Central Processing Unit . . . . . . . . . . . . . . . . . 31 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Section 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . 49 Section 7. Parallel Input/Output (I/O) . . . . . . . . . . . . . . 55 Section 8. 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Section 9. Synchronous Serial Interface (SSI) . . . . . . . . 69 Section 10. Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Section 11. Dual Phase-Locked Loop (PLL) . . . . . . . . . . 85 Section 12. Pulse Width Modulator (PWM) . . . . . . . . . . 93 Section 13. Comparators . . . . . . . . . . . . . . . . . . . . . . . . 99 Section 14. Miscellaneous Register . . . . . . . . . . . . . . . 105 Section 15. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 107 Section 16. Electrical Specifications . . . . . . . . . . . . . . 125 Section 17. Mechanical Specifications . . . . . . . . . . . . 133 Section 18. Ordering Information . . . . . . . . . . . . . . . . . 137 MC68HC05CT4 -- Rev. 2.0 List of Sections For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. List of Sections REQUIRED NON-DISCLOSURE General Release Specification List of Sections For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Table of Contents Section 1. General Description Freescale Semiconductor, Inc... 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.9 Section 2. Memory 2.1 2.2 2.3 2.4 2.5 2.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .25 ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .26 MC68HC05CT4 -- Rev. 2.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 VDD2 and VSS2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . .21 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Port A (PA0-PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Port B (PB0-PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Port C (PC0-PC7/PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Port D (PD0/CMP3+, PD1/CMP1-, PD2/CMP12+, PD3/CMP2-, PD4/SDIO, PD5/SCK, and PD6/TCMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.10 TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.11 FinT and FinR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.4.12 PDoutT and PDoutR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 AGREEMENT REQUIRED Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 3. Central Processing Unit 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Freescale Semiconductor, Inc... AGREEMENT Section 4. Interrupts 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 SSI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Comparator 3 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 NON-DISCLOSURE Section 5. Resets 5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.3 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .46 5.4.2.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2.3 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2.4 COP Watchdog Timer Considerations . . . . . . . . . . . . . . .47 5.4.2.5 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.4.3 Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Table of Contents Section 6. Operating Modes 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Stop Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Low-Power Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Freescale Semiconductor, Inc... Section 7. Parallel Input/Output (I/O) 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Input/Output Port Pin Programming . . . . . . . . . . . . . . . . . . . . .57 Section 8. 16-Bit Timer 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Output Compare Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Timer Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Section 9. Synchronous Serial Interface (SSI) 9.1 9.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 MC68HC05CT4 -- Rev. 2.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Table of Contents REQUIRED 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.7 Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Serial Data In/Out (SDIO) . . . . . . . . . . . . . . . . . . . . . . . . . .71 SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 SSI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 SSI Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Freescale Semiconductor, Inc... AGREEMENT Section 10. Core Timer 10.1 10.2 10.3 10.4 10.5 10.6 10.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .81 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .83 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .84 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Core Timer Power Supply Source . . . . . . . . . . . . . . . . . . . . . .84 NON-DISCLOSURE Section 11. Dual Phase-Locked Loop (PLL) 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.3.1 Dual Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.3.2 12-Bit Reference Counter Modulus Register. . . . . . . . . . . .89 11.3.3 16-Bit Transmit Counter Modulus Register . . . . . . . . . . . . .90 11.3.4 16-Bit Receive Counter Modulus Register . . . . . . . . . . . . .91 11.4 PLL Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Section 12. Pulse Width Modulator (PWM) 12.1 12.2 12.3 12.4 12.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 PWM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 PWM During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Table of Contents 12.6 12.7 12.8 PWM During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PWM During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PWM Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Section 13. Comparators 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Comparator Control/Status Register. . . . . . . . . . . . . . . . . . . .101 Reading Comparator Outputs. . . . . . . . . . . . . . . . . . . . . . . . .103 Comparator During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . .103 Comparator During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . .103 Comparator Power Supply Source . . . . . . . . . . . . . . . . . . . . .103 Freescale Semiconductor, Inc... Section 14. Miscellaneous Register 14.1 14.2 14.3 14.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Miscellaneous Control Register . . . . . . . . . . . . . . . . . . . . . . .105 Miscellaneous Register Power Supply Source . . . . . . . . . . . .106 Section 15. Instruction Set 15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 15.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 15.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 15.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 15.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 15.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 15.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 15.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 15.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 15.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 15.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 15.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .112 15.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .113 15.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .114 15.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .116 15.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 MC68HC05CT4 -- Rev. 2.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Table of Contents REQUIRED 15.5 15.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Section 16. Electrical Specifications 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .128 3.3 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .129 3.3 V and 5.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . .130 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 PLL Signal Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Freescale Semiconductor, Inc... AGREEMENT Section 17. Mechanical Specifications 17.1 17.2 17.3 17.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 44-Lead Plastic-Leaded Chip Carrier (Case 777-02) . . . . . . .134 44-Lead Quad Flat Pack (Case 824A-01) . . . . . . . . . . . . . . .135 NON-DISCLOSURE Section 18. Ordering Information 18.1 18.2 18.3 18.4 18.5 18.6 18.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .138 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .139 ROM Verification Units (RVUs) . . . . . . . . . . . . . . . . . . . . . . .140 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 List of Figures Figure 1-1 1-2 1-3 1-4 2-1 2-2 3-1 3-2 4-1 4-2 5-1 5-2 5-3 6-1 6-2 6-3 7-1 7-2 8-1 8-2 8-3 Title Page Freescale Semiconductor, Inc... MC68HC05CT4 8-K Memory Map . . . . . . . . . . . . . . . . . . . .27 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .38 IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .39 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 RESET and POR Timing Diagram . . . . . . . . . . . . . . . . . . . .45 COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . .48 Single-Chip Mode Pinout of the MC68HC05CT4 . . . . . . . . .51 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .52 STOP/WAIT Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Port C Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .61 Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .64 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .65 MC68HC05CT4 -- Rev. 2.0 List of Figures For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT MC68HC05CT4 Block Diagram . . . . . . . . . . . . . . . . . . . . . .18 44-Lead PLCC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 44-Lead QFP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 REQUIRED Freescale Semiconductor, Inc. List of Figures Figure 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 11-6 12-1 12-2 12-3 13-1 13-2 14-1 16-1 Title Page SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Serial I/O Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 SSI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . .73 SSI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . .75 SSI Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .80 Core Timer Control and Status Register (CTCSR) . . . . . . .81 Core Counter Register (CTCR) . . . . . . . . . . . . . . . . . . . . . .83 Dual PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Dual PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .87 12-Bit Reference Counter (PLLRC) . . . . . . . . . . . . . . . . . . .89 16-Bit Transmit Counter (PLLTX) . . . . . . . . . . . . . . . . . . . . .90 16-Bit Receive Counter (PLLRX) . . . . . . . . . . . . . . . . . . . . .91 Counter Structure Block Diagram. . . . . . . . . . . . . . . . . . . . .92 PWM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 PWM Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 PWM Data Register (PWMDR) . . . . . . . . . . . . . . . . . . . . . .96 Comparator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .100 Comparator Control/Status Register (CMPCSR) . . . . . . . .101 Miscellaneous Control Register (MISCR). . . . . . . . . . . . . .105 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . .132 Freescale Semiconductor, Inc... MC68HC05CT4 -- Rev. 2.0 List of Figures For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 List of Tables Table 4-1 Title Page Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . . .36 COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . .48 Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .49 I/O PIn Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 SSI Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Freescale Semiconductor, Inc... 5-1 6-1 7-1 9-1 10-1 RTI and COP Rates at 2.048 MHz . . . . . . . . . . . . . . . . . . . . . .82 11-1 PLL Reference Counter Select . . . . . . . . . . . . . . . . . . . . . . . . .87 15-1 15-2 15-3 15-4 15-5 15-6 15-7 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . .112 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .113 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .115 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .116 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 18-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 MC68HC05CT4 -- Rev. 2.0 List of Tables For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. List of Tables REQUIRED NON-DISCLOSURE General Release Specification List of Tables For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Freescale Semiconductor, Inc... 1.3 1.2 Introduction The MC68HC05CT4 is a 44-pin member of the MC68HC05 Family of microcontrollers (MCUs), which supports cordless telephone applications. The memory map includes 5376 bytes of on-chip ROM and 256 bytes of RAM. The microcontroller unit has three 8-bit input/output (I/O) ports: A, B, and C; and one 7-bit I/O port: D. Port C has pullup options and keyscan capability. The MC68HC05CT4 includes a bird core, a bird timer, a synchronous serial interface (SSI), 16-bit timer, a MC68HC05CT4 -- Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 1.4 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.4.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.4.2 VDD2 and VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.4.3 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . .21 1.4.4 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.5 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.6 Port A (PA0-PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.7 Port B (PB0-PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.8 Port C (PC0-PC7/PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.9 Port D (PD0/CMP3+, PD1/CMP1-, PD2/CMP12+, PD3/CMP2-, PD4/SDIO, PD5/SCK, and PD6/TCMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.10 TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.11 FinT and FinR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.4.12 PDoutT and PDoutR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED dual 60-MHz phase-locked loop (PLL), pulse width modulator (PWM), and an on-chip computer operating properly (COP) watchdog circuit. Features of the MC68HC05CT4 include: * * * * Low Cost HC05 Core 44-Pin Plastic Leaded Chip Carrier (PLCC) Package 10.24-MHz On-Chip Crystal Oscillator 2.048-MHz Internal CPU Speed 5136 Bytes of User ROM 240 Bytes of Self-Check ROM 256 Bytes of On-Chip RAM 16-Bit Timer 31 Bidirectional I/O Lines Power-Saving Stop and Wait Modes Core Timer Dual 60-MHz PLL Simple Serial with Bidirectional Data (SSI) Keyscan Interrupt with Pullups on Port C Mask Selectable Options: - COP Watchdog Timer - Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger - Port C Pullups for Keyscan - 1-Channel, 6-Bit Pulse Width Modulator (PWM) Three Comparators ROM Security Feature Freescale Semiconductor, Inc... AGREEMENT * * * * * * * * * * * * NON-DISCLOSURE * * General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Description Mask Options 1.3 Mask Options The MC68HC05CT4 has eight mask options: * * * Six port C pullups The IRQ sensitivity COP enable/disable These are nonprogrammable options in that they are selected at the time of code submission when masks are made. These options are: Freescale Semiconductor, Inc... PC7PU -- Port C7 Pullup This bit enables or disables the pullup on port C bit 7. 1 = Enables the pullup 0 = Disables the pullup NOTE: Since port C bit 7 also is shared with the PWM output, PC7PU cannot be selected if PWM output is needed. PC6PU -- Port C6 Pullup This option enables or disables the pullup on port C bit 6. 1 = Enables pullup 0 = Disables pullup PC5PU -- Port C5 Pullup This option enables or disables the pullup on port C bit 5. 1 = Enables pullup 0 = Disables pullup PC4PU -- Port C4 Pullup This option enables or disables the pullup on port C bit 4. 1 = Enables pullup 0 = Disables pullup PC23PU -- Port C Bits 2 and 3 Pullups When PC23PU = 1, the pullups on port C bits 2 and 3 are enabled simultaneously. When PC23PU = 0, the pullups on port C bits 2 and 3 are disabled simultaneously. MC68HC05CT4 -- Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED 60-MHz DUAL PLL OSC1 OSC2 TCAP 10.24 MHz OSCILLATOR 16-BIT TIMER SYSTEM RX PLL SYNTH RxPDout FinR VDD2 VSS2 /5 / 40 INTERNAL PROCESSOR CLOCK DATA DIRECTION REGISTER PD6/TCMP PD5/SCK PORT D PD4/SDIO PWM SSI TX PLL SYNTH TxPDout FinT Freescale Semiconductor, Inc... AGREEMENT PD2/CMP12+ PD1/CMP1- PD0/CMP3+ PC7/PWM PC6 PC5 PC4 PC3 PC2 PC1 PC0 COMPARATORS PD3/CMP2- PA0 DATA DIRECTION REGISTER CORE TIMER SYSTEM PA1 PA2 PORT A PA3 PA4 PA5 PA6 PA7 PB0 DATA DIRECTION REGISTER PB1 PB2 PORT B PB3 PB4 PB5 PB6 PB7 DATA DIRECTION REGISTER COP SYSTEM NON-DISCLOSURE RESET IRQ CPU CONTROL M68HC05 CPU CPU REGISTERS ACCUMULATOR INDEX REGISTER STACK POINTER PROGRAM COUNTER CONDITION CODE REG ROM -- 5378 BYTES ALU KEYBOARD SYSTEM PORT C SRAM -- 256 BYTES VDD VSS Figure 1-1. MC68HC05CT4 Block Diagram General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Description Mask Options PC01PU -- Port C Bits 0 and 1 Pullups When PC01PU = 1, the pullups on port C bits 0 and 1 are enabled simultaneously. When PC01PU = 0, the pullups on port C bits 0 and 1 are disabled simultaneously. COP -- COP Enable When the COP option is selected, the COP watchdog timer is enabled. Freescale Semiconductor, Inc... IRQ -- IRQ Sensitivity When the IRQ option is selected (IRQEN = 1), edge- and levelsensitive IRQ is enabled. When the IRQ option is deselected (IRQEN = 0), edge-only sensitive IRQ is enabled. NOTE: A line over a signal name indicates an active-low signal. For example, RESET is active low. MC68HC05CT4 -- Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT When the COP option is deselected, the COP watchdog timer is disabled. REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED RESET 6 PA3 PA2 PA1 PA0 PB0 PB1 PB2 12 7 1 VDD PC0 PA4 PA5 PA6 PA7 IRQ VSS PC1 PC2 40 39 PC3 PC4 PC5 PC6 PC7/PWM 34 TCAP PD6/TCMP PD5/SCK PD4/SDIO PD3/CMP2- AGREEMENT Freescale Semiconductor, Inc... PB3 PB4 PB5 PB6 17 18 FinT PDouT PDoutR PB7 VDD2 23 VSS2 FinR PD0/CMP3+ OSC1 OSC2 28 PD1/CMP1- 29 PD2/CMP12+ Figure 1-2. 44-Lead PLCC Pinout RESET PC0 PC1 35 PC2 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 VDD IRQ PA4 PA5 PA6 PA7 VSS NON-DISCLOSURE PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 1 2 3 4 5 6 7 8 9 10 11 36 PC3 PC4 PC5 PC6 PC7 TCAP PD6/TCMP PD5/SCK PD4/SDIO PD3/CMP2- PD2/CMP12+ PD0/CMP3+ PB7 PDoutT PDoutR VSS2 FinT FinR Figure 1-3. 44-Lead QFP Pinout General Release Specification General Description For More Information On This Product, Go to: www.freescale.com PD1/CMP1- VDD2 OSC1 OSC2 MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Description Signal Description 1.4 Signal Description The following paragraphs describe the signals. 1.4.1 VDD and VSS Power is supplied to the microcontroller's digital circuits using these two pins. VDD is the positive supply and VSS is ground. Freescale Semiconductor, Inc... 1.4.2 VDD2 and VSS2 Power is supplied to noise-susceptible circuitry such as the phaselocked loop (PLL), comparators, and oscillators that require "cleaner" supplies using these two pins. VDD2 is the positive supply and VSS2 is ground. 1.4.3 Maskable Interrupt Request (IRQ) This pin has a mask option as specified by the user that provides one of two different choices of interrupt triggering sensitivity. The options are: 1. Negative edge-sensitive triggering only 2. Both negative edge-sensitive and level-sensitive triggering The microcontroller unit (MCU) completes the current instruction before it responds to the interrupt request. When IRQ goes low for at least one tILIH, a logic 1 is latched internally to signify that an interrupt has been requested. When the MCU completes its current instruction, the interrupt latch is tested. If the interrupt latch contains a logic 1 and the interrupt mask bit (I bit) in the condition code register is clear, the MCU then begins the interrupt sequence. If the option is selected to include level-sensitive triggering, the IRQ input requires an external resistor to VDD for wire-OR operation. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. MC68HC05CT4 -- Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED NOTE: The voltage on the IRQ pin affects the mode of operation. See Section 6. Operating Modes. 1.4.4 OSC1 and OSC2 These pins provide control input for an on-chip clock oscillator circuit that drives the PLL reference source. A crystal resonator, a ceramic resonator, or an external signal connects to these pins providing a system clock. The oscillator frequency is selectable between 5 or 40 times the internal bus rate. Typical oscillator configurations and component values are shown in Figure 1-4. The manufacturer of the crystal should be consulted, since actual component values are dependent on the type of crystal used. Freescale Semiconductor, Inc... AGREEMENT MCU OSC1 OSC2 OSC1 MCU OSC2 10 M UNCONNECTED < EXTERNAL CLOCK 15 pF 10.24 MHz 15 pF NON-DISCLOSURE (a) Crystal/Ceramic Resonator Oscillator Connections (b) External Clock Source Connections Figure 1-4. Oscillator Connections 1.4.5 Reset (RESET) This active-low pin is used to reset the MCU to a known startup state by pulling RESET low. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See Section 5. Resets. General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Description Signal Description 1.4.6 Port A (PA0-PA7) These eight I/O lines comprise port A. The state of any pin is software programmable, and all port A lines are configured as input during poweron or reset. 1.4.7 Port B (PB0-PB7) These eight I/O lines comprise port B. The state of any pin is software programmable and all port B lines are configured as input during poweron or reset. Freescale Semiconductor, Inc... 1.4.8 Port C (PC0-PC7/PWM) These eight I/O lines comprise port C. All port C lines are configured as input during power-on or reset. Port C has pullup devices and interrupt capability by pin; however, the state of any pin is determined by the user at the time of code submission. For a detailed description of I/O programming, refer to 7.7 Input/Output Port Pin Programming. PC7 is shared with the output of the pulse-width modulation (PWM) function. 1.4.9 Port D (PD0/CMP3+, PD1/CMP1-, PD2/CMP12+, PD3/CMP2-, PD4/SDIO, PD5/SCK, and PD6/TCMP) These seven port lines comprise port D. The state of any pin is software programmable and the lines are configured as input during power-on or reset. PD4 and PD5 are shared with the SSI subsystem, PD6 is shared with the 16-bit timer subsystem, and PD0-PD3 are shared with the comparators. For a detailed description on I/O programming, refer to 7.7 Input/Output Port Pin Programming. 1.4.10 TCAP This pin is used for the16-bit timer input capture operation. Depending on the value of the IEDG bit in the timer control register (TCR), the appropriate level of transition on TCAP will be monitored. When the MC68HC05CT4 -- Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED correct level of transition has occurred, the free-running counter will be transferred to the input capture register. 1.4.11 FinT and FinR These pins are inputs to the PLL transmit and the receive counters, respectively. They typically are driven by the loop VCO and are also AC-coupled. The minimum input signal level is 200 mV peak to peak @ 60.0 MHz. Freescale Semiconductor, Inc... AGREEMENT 1.4.12 PDoutT and PDoutR These PLL pins are 3-state outputs of the transmit and receive phase detectors, respectively, for use as either loop error signals or phase detector signals. NON-DISCLOSURE General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 2. Memory 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .25 ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .26 Freescale Semiconductor, Inc... 2.3 2.4 2.5 2.6 2.2 Introduction This section describes the organization of the on-chip memory. The MC68HC05CT4 8-Kbyte memory map is shown in Figure 2-1 and the input/output (I/O) registers in Figure 2-2. 2.3 Memory Map The MC68HC05CT4 has an 8-Kbyte memory map consisting of user read-only memory (ROM), random-access memory (RAM), self-check ROM, and I/O. 2.4 Read-Only Memory (ROM) The user ROM consists of 5120 bytes of ROM located from $0B00 to $1EFF and 16 bytes of user vectors located from $1FF0 to $1FFF. The self-check ROM is located from $1F00 to $1FEF. MC68HC05CT4 -- Rev. 2.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Memory REQUIRED Twelve of the user vectors, $1FF4-$1FFF, are dedicated to reset and interrupt vectors. The four remaining locations -- $1FF0, $1FF1, $1FF2, and $1FF3 -- are general-purpose user ROM locations. 2.5 ROM Security Feature A security feature has been incorporated into the MC68HC05CT4 to help prevent external viewing of the ROM contents. This feature aids in maintaining the security of proprietary information in customerdeveloped software.1 Freescale Semiconductor, Inc... AGREEMENT 2.6 Random-Access Memory (RAM) The user RAM consists of 256 bytes of a shared stack area. The RAM starts at address $0030 and ends at address $012F. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. NOTE: NON-DISCLOSURE Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM difficult for unauthorized users. General Release Specification Memory For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Memory Random-Access Memory (RAM) $0000 $0022 $0023 $002F $0030 I/O 35 Bytes Reserved 13 Bytes RAM 208 Bytes $0000 Ports 8 Bytes Core Timer 2 Bytes PLL 8 Bytes Reserved 1 Byte Timer 10 Bytes SSI 3 Bytes Reserved PWM 1 Byte Miscellaneous 1 Byte Comparators 1 Byte Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register Core Timer Control/Status Register Core Timer Counter Register PLL Control Register PLL Ref. Counter MSB PLL Ref. Counter LSB Transmit PLL MSB Transmit PLL LSB Receive PLL MSB Receive PLL LSB Reserved Timer Control Register Timer Status Register $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $00C0 $00FF $0100 $012F $0130 Stack 64 Bytes RAM 48 Bytes Unused 2512 Bytes Freescale Semiconductor, Inc... $0AFF $0B00 User ROM 5120 Bytes $1EFF $1F00 $1F01 $1FEF $1FF0 $1FFF Self-Check ROM 240 Bytes ROM User Vectors 16 Bytes $0022 Input Capture MSB Input Capture LSB Output Compare MSB Output Compare LSB Counter MSB Counter LSB Alternate Counter MSB Alternate Counter LSB SSI Status Register SSI Data Register SSI Control Register Reserved PWM Data Register Miscellaneous Register Comparator Control/Status Register $18 $19 $1A $1B $1C $1D $1E $1F $20 $21 $22 Figure 2-1. MC68HC05CT4 8-K Memory Map MC68HC05CT4 -- Rev. 2.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE $17 AGREEMENT REQUIRED Freescale Semiconductor, Inc. Memory REQUIRED Addr $00 $01 $02 $03 $04 $05 Register Name Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register Bit 7 6 5 4 3 2 1 0 0 Freescale Semiconductor, Inc... AGREEMENT $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 0 RTIF TOFE RTIE TOFC RTFC RT1 RT0 Timer Control and Status Register CTOF Timer Counter Register PLL Control Register PLL Reference Counter -- MSB PLL Reference Counter -- LSB PLL Transmit Counter -- MSB PLL Transmit Counter -- LSB PLL Receive Counter -- MSB PLL Receive Counter -- LSB Reserved Timer Control Register Timer Status Register Timer Input Capture -- MSB Timer Input Capture -- LSB Timer Output Compare -- MSB TImer Output Compare -- LSB Timer Counter -- MSB Timer Counter -- LSB R ICIE ICF 0 0 TLOCK RLOCK REFON 0 0 0 TXON RXON PLS1 PLS0 NON-DISCLOSURE R OCIE OCF R TOIE 0 R 0 0 R 0 0 R TON 0 R IEDGE 0 R OLVL 0 R = Reserved Figure 2-2. I/O Registers General Release Specification Memory For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Memory Random-Access Memory (RAM) Addr $1A $1B $1C $1D $1E $1F Register Name Timer Alternate Counter -- MSB TImer Alternate Counter -- LSB SSI Status Register SSI Data Register SSI Control Register Reserved PWM Data Register Miscellaneous Register Bit 7 6 5 4 3 2 1 0 SF DCOL 0 0 0 0 0 0 SIE R 0 0 SE R 0 0 CMP2 LSBF R MSTR R CPOL R T/R R SR1 R SR0 R Freescale Semiconductor, Inc... $20 $21 $22 0 CMP1 0 CM3IE SPEED CM3IC COE CEN3 PWME CEN2 0 CEN1 Comparator Control/Status Register CMP3 R = Reserved Figure 2-2. I/O Registers (Continued) MC68HC05CT4 -- Rev. 2.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Memory REQUIRED NON-DISCLOSURE General Release Specification Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 3. Central Processing Unit 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Freescale Semiconductor, Inc... 3.3 3.4 3.5 3.6 3.7 3.2 Introduction The MCU contains five registers as shown in Figure 3-1. The interrupt stacking order is shown in Figure 3-2. 7 A 7 X 12 PC 12 0 0 0 0 0 7 1 1 SP CCR H I N Z C CONDITION CODE REGISTER 0 STACK POINTER 0 PROGRAM COUNTER 0 INDEX REGISTER 0 ACCUMULATOR Figure 3-1. Programming Model MC68HC05CT4 -- Rev. 2.0 Central Processing Unit For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Central Processing Unit REQUIRED 7 1 INCREASING MEMORY ADDRESSES R E T U R N 1 1 0 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL STACK I N T E R R U P T DECREASING MEMORY ADDRESSES UNSTACK NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. Freescale Semiconductor, Inc... AGREEMENT Figure 3-2. Stacking Order 3.3 Accumulator The accumulator (A) is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 7 A 0 NON-DISCLOSURE 3.4 Index Register The index register (X) is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area. 7 X 0 General Release Specification Central Processing Unit For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Central Processing Unit Condition Code Register 3.5 Condition Code Register The condition code register (CCR) is a 5-bit register in which the H, N, Z, and C bits are used to indicate the results of the instruction just executed, and the I bit is used to enable interrupts. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. CCR H I N Z C Freescale Semiconductor, Inc... Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the I bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/Borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit also is affected during bit test and branch instructions and during shifts and rotates. MC68HC05CT4 -- Rev. 2.0 Central Processing Unit For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Central Processing Unit REQUIRED 3.6 Stack Pointer The stack pointer contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer then is decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the seven most significant bits (MSB) are permanently set to 0000011. These seven bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 12 0 0 0 0 0 7 1 0 1 SP Freescale Semiconductor, Inc... AGREEMENT 3.7 Program Counter The program counter (PC) is a 13-bit register that contains the address of the next byte to be fetched. . 12 PC 0 NON-DISCLOSURE NOTE: The HC05 CPU core is capable of addressing 16-bit locations. For this implementation, however, the addressing registers are limited to an 8-Kbyte memory map General Release Specification Central Processing Unit For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 4. Interrupts 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 SSI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Comparator 3 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Freescale Semiconductor, Inc... 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.2 Introduction The MCU can be interrupted seven different ways: 1. Nonmaskable software interrupt instruction (SWI) 2. External asynchronous interrupt (IRQ) 3. External interrupt via IRQ on PC0-PC7 4. Internal 16-bit timer interrupt (TIMER) 5. Internal synchronous serial interface (SSI) interrupt 6. Internal core timer interrupt 7. Comparator 3 MC68HC05CT4 -- Rev. 2.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED 4.3 CPU Interrupt Processing Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I bit in the CCR is clear) and the corresponding interrupt enable bit is set, the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs, the processor completes the current instruction, stacks the current CPU register states, sets the I bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending after the stacking operation, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. When an interrupt is to be processed, the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $1FF4-$1FFF as defined in Table 4-1. Table 4-1. Vector Address for Interrupts and Reset Register N/A N/A CMCSR TSR SSSR CTCSR Flag Name N/A N/A CMP3 OCF, ICF, TOF SSIF TOFE, RTIE Reset Software CMP3, External Interrupts* 16-bit Timer Interrupts SSI Interrupt Core Timer Interrupts Interrupt CPU Interrupt RESET SWI CMP3/IRQ TIMER SSI TIMER, RTI Vector Address $1FFE-$1FFF $1FFC-$1FFD $1FFA-$1FFB $1FF8-$1FF9 $1FF6-$1FF7 $1FF4-$1FF5 NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT * External interrupts include IRQ and PORTC sources. General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Interrupts Reset Interrupt Sequence The M68HC05 CPU does not support interruptible instructions. The maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. Latency = (Longest instruction execution time + 10) x tcyc seconds A return-to-interrupt (RTI) instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occurs during interrupt processing. Freescale Semiconductor, Inc... 4.4 Reset Interrupt Sequence The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low-level input on the RESET pin or an internally generated RST signal causes the program to vector to its starting address, which is specified by the contents of memory locations $1FFE and $1FFF. The I bit in the condition code register is also set. The MCU is configured to a known state during this type of reset as described in 4.3 CPU Interrupt Processing. 4.5 Software Interrupt (SWI) The SWI is an executable instruction and a nonmaskable interrupt since it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), the SWI instruction executes after interrupts that were pending before the SWI was fetched or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD. MC68HC05CT4 -- Rev. 2.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED FROM RESET Y I BIT IN CCR SET? N IRQ EXTERNAL INTERRUPT CMP3 N INTERNAL 16-BIT TIMER INTERRUPT N INTERNAL SSI INTERRUPT N INTERNAL CORE TIMER INTERRUPT N Y Y Y CLEAR IRQ REQUEST LATCH Freescale Semiconductor, Inc... AGREEMENT Y NON-DISCLOSURE STACK PC, X, A, CCR FETCH NEXT INSTRUCTION SET I BIT IN CC REGISTER SWI INSTRUCTION ? N Y RTI INSTRUCTION ? N RESTORE REGISTERS FROM STACK: CCR, A, X, PC EXECUTE INSTRUCTION Y LOAD PC FROM APPROPRIATE VECTOR Figure 4-1. Interrupt Processing Flowchart General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Interrupts Hardware Interrupts 4.6 Hardware Interrupts All hardware interrupts except RESET are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. The two types of hardware interrupts are explained in the following sections. 4.7 External Interrupt (IRQ) Freescale Semiconductor, Inc... NOTE: The BIH and BIL instructions will apply only to the level on the IRQ pin itself, and not to the output of the logic OR function with the port C IRQ interrupts. The state of the individual port C pins can be checked by reading the appropriate port C pins as inputs. TO BIH & BIL INSTRUCTION SENSING IRQ LATCH R IRQ PIN VDD PORT C IRQ VECTOR FETCH RST LEVEL (MASK OPTION) Figure 4-2. IRQ Function Block Diagram The IRQ pin is one source of an external interrupt. All port C pins (PC0-PC7) act as other external interrupt sources if the keyscan feature is enabled as specified by the user. When edge sensitivity is selected for the IRQ interrupt, it is sensitive to: * * Falling edge on the IRQ pin Falling edge on any port C pin with keyscan enabled MC68HC05CT4 -- Rev. 2.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE TO IRQ PROCESSING IN CPU AGREEMENT The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown in Figure 4-2. REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED When edge and level sensitivity is selected for the IRQ interrupt, it is sensitive to the following cases: * * * Low level on the IRQ pin Falling edge on the IRQ pin Falling edge or low level on any port C pin with keyscan enabled 4.8 External Interrupt Timing Freescale Semiconductor, Inc... AGREEMENT If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of the IRQ source. The interrupt request is then synchronized internally and serviced as specified by the contents of $1FFA and $1FFB. Either a level-sensitive and edge-sensitive trigger or an edge-sensitiveonly trigger is available via the mask programmable option for the IRQ pin. 4.9 16-Bit Timer Interrupt Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). Any of these interrupts vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1FF8 and $1FF9. NON-DISCLOSURE 4.10 SSI Interrupt Two different synchronous serial interrupt (SSI) flags cause an SSI interrupt whenever they are set and enabled. The interrupt flags are in the SSI status register (SSSR), and the enable bits are in the SSI control register (SSCR). Either of these interrupts vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1FF6 and $1FF7. General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Interrupts Core Timer Interrupt 4.11 Core Timer Interrupt This timer can create two types of interrupts. A timer overflow interrupt occurs whenever the 8-bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real-time interrupt occurs whenever the programmed time elapses and the enable bit RTIE is set. Either of these interrupts vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1FF4 and $1FF5. Freescale Semiconductor, Inc... 4.12 Comparator 3 Interrupt Comparator 3 can create an interrupt when its output (CMP3) gets set and the enable bit CM3IE is set. The interrupt service routine is located at the address specified by the contents of memory locations $1FFA and $1FFB. MC68HC05CT4 -- Rev. 2.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED NON-DISCLOSURE General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 5. Resets 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Freescale Semiconductor, Inc... 5.3 5.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .46 5.4.2.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2.3 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2.4 COP Watchdog Timer Considerations . . . . . . . . . . . . . . .47 5.4.2.5 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.4.3 Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 The MCU can be reset from four sources: one external input and three internal restart conditions. The RESET pin is an input with a Schmitt trigger as shown in Figure 5-1. All the internal peripheral modules will be reset by the internal reset signal (RST). Refer to Figure 5-2 for reset timing detail. 5.3 External Reset (RESET) The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active-low input will generate the RST signal and MC68HC05CT4 -- Rev. 2.0 Resets For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 5.2 Introduction AGREEMENT REQUIRED Freescale Semiconductor, Inc. Resets REQUIRED reset the CPU and peripherals. Termination of the external RESET input or the internal COP watchdog reset are the only reset sources that can alter the operating mode of the MCU. NOTE: Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified. AGREEMENT Freescale Semiconductor, Inc... IRQ/VTST D LATCH RESET R CLOCKED TO IRQ LOGIC MODE SELECT OSC DATA ADDRESS COP WATCHDOG (COPR) CPU S D LATCH PH2 TO OTHER PERIPHERALS VDD POWER-ON RESET (POR) ILLEGAL ADDRESS (ILLADDR) RST NON-DISCLOSURE ADDRESS Figure 5-1. Reset Block Diagram General Release Specification Resets For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc... V DD > VPOR 4 0V MC68HC05CT4 -- Rev. 2.0 tCYC 1FFE 1FFF NEW PC NEW PC 1FFE 1FFE 1FFE 1FFE 1FFF NEW PC NEW PC NEW PCH NEW PCL OP CODE PCH t RL 3 PCL OP CODE OSC12 4064 tCYC INTERNAL PROCESSOR CLOCK1 INTERNAL ADDRESS BUS1 INTERNAL DATA BUS1 Freescale Semiconductor, Inc. Resets For More Information On This Product, Go to: www.freescale.com RESET NOTES: 1. Internal timing signal and bus information not available externally 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. 4. VDD must fall to a level lower than VPOR to be recognized as a power-on reset. General Release Specification Resets External Reset (RESET) Figure 5-2. RESET and POR Timing Diagram NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Resets REQUIRED 5.4 Internal Resets The three internally generated resets are the initial power-on reset function, the COP watchdog timer reset, and the illegal address detector. Termination of the external RESET input or the internal COP watchdog timer are the only reset sources that can alter the operating mode of the MCU. The other internal resets do not have any effect on the mode of operation when their reset state ends. AGREEMENT Freescale Semiconductor, Inc... 5.4.1 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor bus clock cycles (PH2) after the oscillator becomes active. The POR generates the RST signal that resets the CPU. If any other reset function is active at the end of this 4064-cycle delay, the RST signal remains in the reset condition until the other reset condition(s) end. During the POR, the RESET pin is forced low. NON-DISCLOSURE 5.4.2 Computer Operating Properly Reset (COPR) The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to time out, an internal reset is generated to reset the MCU. Regardless of an internal or external RESET, the MCU comes out of a COP reset according to the standard rules of mode selection. The COP reset function is enabled or disabled by a mask option and is verified during production testing. 5.4.2.1 Resetting the COP Writing a zero to the COPF bit prevents a COP reset. This action resets the counter and begins the timeout period again. The COPF bit is bit 0 General Release Specification Resets For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Resets Internal Resets of address $1FF0. A read of address $1FF0 returns user data programmed at that location. 5.4.2.2 COP During Wait Mode The COP continues to operate normally during wait mode. The software should pull the device out of wait mode periodically and reset the COP by writing to the COPF bit to prevent a COP reset. 5.4.2.3 COP During Stop Mode When the stop enable mask option is selected, stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. When STOP is executed, the COP counter will hold its current state. If a reset is used to exit stop mode, the COP counter is reset and held until 4064 POR cycles are completed, at that time, counting will begin. If an external IRQ is used to exit stop mode, the COP counter does not wait for the completion of the 4064 POR cycles but it does count these cycles. It is recommended, therefore, that the COP is fed before executing the STOP instruction. 5.4.2.4 COP Watchdog Timer Considerations The COP watchdog timer is active in all modes of operation if enabled by a mask option. If the COP watchdog timer is selected by a mask option, any execution of the STOP instruction (either intentional or inadvertent due to the CPU being disturbed) causes the oscillator to halt and prevent the COP watchdog timer from timing out. If the COP watchdog timer is selected by a mask option, the COP resets the MCU when it times out. Therefore, it is recommended that the COP watchdog is disabled for a system that must have intentional uses of the wait mode for periods longer than the COP timeout period. The recommended interactions and considerations for the COP watchdog timer, STOP instruction, and WAIT instruction are summarized in Table 5-1. Freescale Semiconductor, Inc... MC68HC05CT4 -- Rev. 2.0 Resets For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Resets REQUIRED Table 5-1. COP Watchdog Timer Recommendations IF the following conditions exist: THEN the COP Watchdog Timer should be: WAIT Time WAIT Time less than COP Timeout WAIT Time More than COP Timeout Any length WAIT Time Enable or Disable COP by Mask Option Disable COP by Mask Option Disable COP by Mask Option Freescale Semiconductor, Inc... AGREEMENT 5.4.2.5 COP Register The COP register is shared with the MSB of an unimplemented user interrupt vector as shown in Figure 5-3. Reading this location returns whatever user data has been programmed at this location. Writing a zero to the COPR bit in this location clears the COP watchdog timer. Addr $1FF0 Register Name Unimplemented Vector Read: and COP Watchdog Timer Write: Bit 7 X 6 X 5 X 4 X 3 X 2 X 1 X Bit 0 X COPR = Unimplemented NON-DISCLOSURE Figure 5-3. COP Watchdog Timer Location 5.4.3 Illegal Address An illegal address reset is generated when the CPU attempts to fetch an instruction from either unimplemented address space ($0130 to $0AFF) or I/O address space ($0000 to $002F). General Release Specification Resets For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 6. Operating Modes 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Freescale Semiconductor, Inc... 6.3 6.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4.2 Stop Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.4.4 Low-Power Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.2 Introduction The MCU has two modes of operation: single-chip mode and self-check mode with two oscillator options. Table 6-1 shows the conditions required to go into each mode. Table 6-1. Operating Mode Conditions RESET IRQ VSS-VDD VTST = 2 x VDD VTST VDD VSS Self-Check PB1 VSS-VDD PD5 VSS-VDD MODE Single-Chip MC68HC05CT4 -- Rev. 2.0 Operating Modes For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Operating Modes REQUIRED 6.3 Single-Chip Mode In single-chip mode, the address and data buses are not available externally, but there are three 8-bit input/output (I/O) ports and one 7-bit I/O port. This mode allows the MCU to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. All address and data activity occurs within the MCU. Singlechip mode is entered on the rising edge of RESET if the IRQ pin is within normal operating range. Freescale Semiconductor, Inc... AGREEMENT 6.4 Low-Power Modes The following paragraphs describe the low-power modes. 6.4.1 Stop Mode The STOP instruction places the MCU in its lowest power-consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation. During stop mode, the CTCSR ($08) bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is cleared. The I bit in the CCR is cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of stop mode only by an external interrupt or reset. NON-DISCLOSURE General Release Specification Operating Modes For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Operating Modes Low-Power Modes 6 PA3 PA2 PA1 PA0 PB0 PB1 PB2 12 7 1 40 39 PC3 PC4 PC5 PC6 PC7/PWM 34 TCAP PD6/TCMP Freescale Semiconductor, Inc... PB4 PB5 PB6 17 18 FinT PDouT VDD2 PDoutR PB7 23 OSC1 OSC2 FinR PD0/CMP3+ VSS2 28 PD1/CMP1- 29 PD4/SDIO PD3/CMP2- PD2/CMP12+ Figure 6-1. Single-Chip Mode Pinout of the MC68HC05CT4 6.4.2 Stop Recovery The processor can be brought out of the stop mode only by an external interrupt or RESET. See Figure 6-2. 6.4.3 Wait Mode The WAIT instruction places the MCU in a low power-consumption mode, but the wait mode consumes more power than the stop mode. All CPU action is suspended, but the core timer, the oscillator, and any enabled module remain active. Any interrupt or reset will cause the MCU to exit the wait mode. The user must shut off subsystems to reduce power consumption. WAIT current specifications assume CPU operation only and do not include current consumption by any other subsystems. MC68HC05CT4 -- Rev. 2.0 Operating Modes For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT PB3 PD5/SCK REQUIRED RESET VDD PC0 PA4 PA5 PA6 PA7 IRQ VSS PC1 PC2 Freescale Semiconductor, Inc. Operating Modes REQUIRED OSC11 tRL RESET IRQ2 tLIH IRQ3 tILCH 4064 tcyc Freescale Semiconductor, Inc... AGREEMENT INTERNAL CLOCK INTERNAL ADDRESS BUS 1FFE 1FFE 1FFE 1FFE 1FFF NOTES: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level- and edge-sensitive mask option RESET OR INTERRUPT VECTOR FETCH Figure 6-2. Stop Recovery Timing Diagram During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The timer may be enabled to allow a periodic exit from wait mode. NON-DISCLOSURE 6.4.4 Low-Power Wait When the wait mode is entered by executing the WAIT instruction, the oscillator divider changes from a divide-by-5 to a divide-by-40 (additional divide-by-8) to lower the wait current. As a result, this gives a CPU clock rate of 256 kHz if the oscillator is running with a 10.24-MHz crystal. The oscillator divide-by-5 or divide-by-40 option is also controlled by the speed bit located in the miscellaneous control register ($21). Section 14. Miscellaneous Register. When returning from wait mode via an interrupt, the OSC rate prior to entering wait mode is restored. General Release Specification Operating Modes For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Operating Modes Low-Power Modes STOP WAIT STOP OSCILLATOR AND ALL CLOCKS CLEAR I BIT OSCILLATOR ACTIVE TIMER CLOCK ACTIVE PROCESSOR CLOCKS STOPPED CLEAR I BIT Freescale Semiconductor, Inc... N RESET RESET N N EXTERNAL INTERRUPT (IRQ) Y Y Y EXTERNAL INTERRUPT (IRQ) Y Y N TIMER INTERRUPT N TURN ON OSCILLATOR WAIT FOR TIME DELAY TO STABILIZE RESTART PROCESSOR CLOCK Y SSI INTERRUPT N Y CORE TIMER INTERRUPTS N Figure 6-3. STOP/WAIT Flowchart MC68HC05CT4 -- Rev. 2.0 Operating Modes For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 1. FETCH RESET VECTOR OR 2 SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Operating Modes REQUIRED NON-DISCLOSURE General Release Specification Operating Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 7. Parallel Input/Output (I/O) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Input/Output Port Pin Programming . . . . . . . . . . . . . . . . . . . . .57 Freescale Semiconductor, Inc... 7.3 7.4 7.5 7.6 7.7 7.2 Introduction In user mode 31 lines are arranged as one 7-bit and three 8-bit ports. Most of these port pins are programmable as either inputs or outputs under software control of the data direction registers, though some are input only. NOTE: To avoid a glitch on the output pins, write data to the I/O port data register before writing a logic 1 to the corresponding data direction register. 7.3 Port A Port A is an 8-bit bidirectional port that does not share any of its pins with other subsystems. The port A data register is at $0000 and the data direction register (DDR) is at $0004. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a logic 1 to a DDR bit sets the corresponding port bit to output mode. MC68HC05CT4 -- Rev. 2.0 Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED 7.4 Port B Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register (DDR) is at $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a logic 1 to a DDR bit sets the corresponding port bit to output mode. Freescale Semiconductor, Inc... AGREEMENT 7.5 Port C Port C is an 8-bit bidirectional port. The port C data register is at $0002 and the data direction register (DDR) is at $0006. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a logic 1 to a DDR bit sets the corresponding port pin to output mode. Each of the port C pins has an optional pullup device. When the DDR bit is cleared and the pullup device is enabled, the pin will be a pullup and an interrupt pin. The edgeor edge- and level-sensitivity of the IRQ pin also pertains to the enabled port C pins. Care needs to be taken when using port C pins that have the pullup enabled. Before switching from an output to an input, the data should be preconditioned to a logic 1 to prevent an interrupt from occurring. Port C bit 7 is also shared with the PWM output. When PC7 is used as the PWM output, its pullup option should not be selected (see Figure 7-1). VDD VDD MASK OPTION (PC7PU) DDR BIT ENABLED IRQ NON-DISCLOSURE DISABLED SCHMITT TRIGGER PC7 NORMAL PORT CIRCUITRY AS SHOWN IN FIGURE 7-2 (PC7 ADDS PWM) FROM ALL OTHER PORT C PINS TO INTERRUPT LOGIC Figure 7-1. Port C Pullup Option General Release Specification Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Port D 7.6 Port D Port D is a 7-bit bidirectional port. Two of its pins are shared with the SSI subsystem, four are shared with the comparators, and one is shared with the timer. During reset, all seven bits become valid input ports because all special function output drivers associated with the timer and SSI subsystems are disabled. 7.7 Input/Output Port Pin Programming Freescale Semiconductor, Inc... Port pins may be programmed as inputs or outputs under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each I/O port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0. At power-on or reset, all DDRs are cleared, which configures all pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. Refer to Table 7-1 and to Figure 7-2 for additional information. Table 7-1. I/O PIn Functions R/W 0 0 1 1 DDR 0 1 0 1 I/O Pin Functions The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in an output mode. The output data latch is read. MC68HC05CT4 -- Rev. 2.0 Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED DATA DIRECTION REGISTER BIT INTERNAL HC05 CONNECTIONS LATCHED OUTPUT DATA BIT OUTPUT I/O PIN INPUT REG BIT Freescale Semiconductor, Inc... AGREEMENT INPUT I/O Figure 7-2. I/O Circuitry NON-DISCLOSURE General Release Specification Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 8. 16-Bit Timer 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Output Compare Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Timer Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Freescale Semiconductor, Inc... 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 The timer consists of a 16-bit, free-running counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements, while simultaneously generating an output waveform. Pulse widths can vary from several microseconds to many seconds. Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. These registers contain the high and low byte of that functional segment. Access to the high byte inhibits that specific timer function until the low byte is also accessed. NOTE: The I bit in the CCR should be set while manipulating both the high and low byte registers of a specific timer function to ensure that an interrupt does not occur. MC68HC05CT4 -- Rev. 2.0 16-Bit Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 8.2 Introduction AGREEMENT REQUIRED Freescale Semiconductor, Inc. 16-Bit Timer REQUIRED 8.3 Counter Register The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1A-$1B (counter alternate register). If a read of the free-running counter or counter alternate register is from the least significant byte (LSB) ($19, $1B), the LSB receives the count value at the time of the read. If a read of the freerunning counter or counter alternate register first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB also must be read to complete the sequence. The counter alternate register differs from the counter register in one respect: a read of the counter register MSB can clear the timer overflow flag (TOF). The counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF. NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT General Release Specification 16-Bit Timer For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. 16-Bit Timer Counter Register INTERNAL BUS INTERNAL PROCESSOR CLOCK /4 HIGH BYTE LOW BYTE HIGH LOW BYTE BYTE $16 OUTPUT $17 COMPARE REGISTER 8-BIT BUFFER HIGH LOW BYTE BYTE $14 INPUT CAPTURE REGISTER $15 16-BIT FREE $18 RUNNING COUNTER $19 COUNTER $1A ALTERNATE REGISTER $1B Freescale Semiconductor, Inc... OUTPUT COMPARE CIRCUIT OVERFLOW DETECT CIRCUIT EDGE DETECT CIRCUIT D Q C TIMER STATUS ICF OCF TOF $13 REG. FOLVL OUTPUT LEVEL REG. CLK TIMER RESET ICIE OCIE TOIE IEDG OLVL CONTROL REG. $12 OUTPUT LEVEL (TCMP) PD6 EDGE INPUT (TCAP) INTERRUPT CIRCUIT The free-running counter is configured to $FFFC during reset and is a read-only register but only when the timer is enabled. During a power-on reset, the counter is also preset to $FFFC and begins running only after the TON bit in the TIMER control register is set. Because the freerunning counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also be enabled when counter roll-over occurs by setting its interrupt enable bit (TOIE). NOTE: The I bit in the CCR should be set while manipulating both the high and low byte registers of a specific timer function to ensure that an interrupt does not occur. MC68HC05CT4 -- Rev. 2.0 16-Bit Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE Figure 8-1. 16-Bit Timer Block Diagram AGREEMENT REQUIRED Freescale Semiconductor, Inc. 16-Bit Timer REQUIRED 8.4 Output Compare Register The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register is used for several purposes, such as indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. The output compare register contents are continually compared with the contents of the free-running counter. If a match is found, the corresponding output compare flag (OCF) bit is set and the corresponding output level (OLVL) bit is clocked to an output level register. The output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCIE) is set. After a processor write cycle to the output compare register containing the MSB ($16), the output compare function is inhibited until the LSB ($17) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register without affecting the other byte. The output level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF) is set or clear. NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT General Release Specification 16-Bit Timer For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. 16-Bit Timer Input Capture Register 8.5 Input Capture Register Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition that triggers the counter transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture register. The result obtained by an input capture is one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register MSB ($14), the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. Freescale Semiconductor, Inc... MC68HC05CT4 -- Rev. 2.0 16-Bit Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. 16-Bit Timer REQUIRED 8.6 Timer Control Register The TCR is a read/write register containing six control bits. Three bits control interrupts associated with the timer status register flags ICF, OCF, and TOF. Address: $0012 Bit 7 Read: ICIE Write: Reset: 0 0 0 0 0 0 0 0 6 OCIE 5 TOIE 4 0 3 0 2 TON 1 IEDG Bit 0 OLVL Freescale Semiconductor, Inc... AGREEMENT Figure 8-2. Timer Control Register (TCR) ICIE -- Input Capture Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled OCIE -- Output Compare Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TOIE -- Timer Overflow Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TON -- Timer On When disabled, the timer is initialized to the reset condition. 1 = Timer enabled 0 = Timer disabled IEDG -- Input Edge Value of input edge determines which level transition on the TCAP pin will trigger a free-running counter transfer to the input capture register. Reset clears this bit. 1 = Positive edge 0 = Negative edge General Release Specification 16-Bit Timer For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 NON-DISCLOSURE Freescale Semiconductor, Inc. 16-Bit Timer Timer Status Register OLVL -- Output Level Value of output level is clocked into the output level register by the next successful output compare and will appear on the TCMP pin. 1 = High output 0 = Low output 8.7 Timer Status Register Freescale Semiconductor, Inc... The TSR is a read-only register containing three status flag bits. Address: $0013 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 ICF 6 OCF 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0 = Unimplemented Figure 8-3. Timer Status Register (TSR) ICF -- Input Capture Flag 1 = Flag set when selected polarity edge is sensed by input capture edge detector 0 = Flag cleared when TSR and input capture low register ($15) are accessed Reset clears this bit. OCF -- Output Compare Flag 1 = Flag set when output compare register contents match the freerunning counter contents 0 = Flag cleared when TSR and output compare low register ($17) are accessed Reset clears this bit. MC68HC05CT4 -- Rev. 2.0 16-Bit Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. 16-Bit Timer REQUIRED TOF -- Timer Overflow Flag 1 = Flag set when free-running counter transitions from $FFFF to $0000 occurs 0 = Flag cleared when TSR and counter low register ($19) are accessed Reset clears this bit. Bits 0-4 -- Not Used Always read zero. Freescale Semiconductor, Inc... AGREEMENT Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit. A problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: * * The timer status register is read or written when TOF is set. The MSB of the free-running counter is read but not for the purpose of servicing the flag. NON-DISCLOSURE The counter alternate register at address $1A and $1B contains the same value as the free-running counter at address $18 and $19; this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. 8.8 Timer During Wait Mode The CPU clock halts during wait mode, but the timer remains active if turned on prior to entering wait mode. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. General Release Specification 16-Bit Timer For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. 16-Bit Timer Timer During Stop Mode 8.9 Timer During Stop Mode In stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. If reset is used, the counter is forced to $FFFC. During stop, if the timer is on and at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags or wake up the MCU. When the MCU does wake up, however, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit stop mode, no input capture flag or data remains, even if a valid input capture edge occurred. Freescale Semiconductor, Inc... 8.10 Timer Power Supply Source The timer's power is supplied by VDD and VSS. VDD2 and VSS2 will not be needed since this module is not susceptible to supply noise. MC68HC05CT4 -- Rev. 2.0 16-Bit Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. 16-Bit Timer REQUIRED NON-DISCLOSURE General Release Specification 16-Bit Timer For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 9. Synchronous Serial Interface (SSI) 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Freescale Semiconductor, Inc... 9.3 Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.3.2 Serial Data In/Out (SDIO) . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.4 SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9.4.1 SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9.4.2 SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 9.4.3 SSI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 9.5 9.6 9.7 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 SSI Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 9.2 Introduction The synchronous serial interface (SSI) is a 2-wire master/slave system including serial clock (SCK) and serial data input/output (SDIO). Data is transferred eight bits at a time. A software programmable option determines whether the SSI transfers data most significant bit (MSB) or least significant bit (LSB) first and an interrupt may be generated at the completion of each transfer. When operating as a master device, the serial clock speed is selectable from a choice of four rates. MC68HC05CT4 -- Rev. 2.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED Transmission in master mode is initiated by a write to the SSI data register (SDR). A transfer cannot be initiated in slave mode; the external master initiates the transfer. The programmer must choose between master or slave mode before the SSI is enabled. The programmer must ensure that only one master exists in the system at any one time. All devices in the system must operate with the same clock polarity and data rates. Slaves should always be disabled before the master is disabled. Freescale Semiconductor, Inc... AGREEMENT MCU INTERNAL BUS INTERRUPT CONTROLS/ADDRESS BUS DATA BUS INTERRUPT CIRCUIT CONTROL LOGIC TO INTERRUPT LOGIC 000000 SSI STATUS REG. SSI CONTROL REG. MSTR CPOL T/R SSI DATA REG. LSBF SR HFF SDIO NON-DISCLOSURE START SF DCOL SE SE CLOCK GENERATOR SCK MSTR & Figure 9-1. SSI Block Diagram General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) Signal Format 9.3 Signal Format The SSI is comprised of two main input/output (I/O) signals that interface with port D serial clock and serial data. 9.3.1 Serial Clock (SCK) When SE = 0, this pin is a port D bit 5 pin, which follows the port D DDR assignment. Freescale Semiconductor, Inc... In master mode (MSTR = 1), the serial clock (SCK) pin is an output with four selectable frequencies. This pin will be high (CPOL = 1) or low (CPOL = 0) between transmissions. In slave mode (MSTR = 0), the SCK pin is an input and the clock must be supplied by an external master with a maximum frequency of fOP/2. There is no minimum SCK frequency. This pin should be driven high (CPOL = 1) or low (CPOL = 0) between transmissions by the external master and must be stable before the SSI is first enabled (SE = 1). Data is always captured at the serial data in/out (SDIO) pin on the rising edge of SCK. Data is always shifted out and presented at the serial data in/out (SDIO) pin on the falling edge of SCK. 9.3.2 Serial Data In/Out (SDIO) Prior to enabling the SSI (SE = 0), the serial data in/out (SDIO) pin is a port D bit 4 pin, which follows the port D DDR assignment. When the SSI is enabled (SE = 1) the SDIO pin becomes a high-impedance input pin if the T/R bit is low or it idles high if the T/R bit is high. The data can be sent or received in either MSB first format (LSBF = 0) or LSB first format (LSBF = 1). If (CPOL = 1), the first falling edge of SCK will shift the first data bit out to the SDIO pin. Subsequent falling edges of SCK will shift the remaining data bits out. MC68HC05CT4 -- Rev. 2.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED If (CPOL = 0), the first data bit will be driven out to the SDIO pin before the first rising edge of SCK. Subsequent falling edges of SCK will shift the remaining data bits out. When receiving data in master mode, the T/R bit must be low and data must be written to the data register to initiate clock generation. When transmitting data in master mode, the T/R bit must be high. When receiving data in slave mode, T/R bit must be low and the clock and data must be supplied by external device. When transmitting data in slave mode, T/R bit must be high, and data must be written to the data register before the SSI is enabled to ensure that proper data is transferred. Freescale Semiconductor, Inc... AGREEMENT SCK (CPOL = 1) SDIO SCK (CPOL = 0) SE BIT 1 BIT 2 BIT 3 BIT 7 BIT 8 NON-DISCLOSURE Figure 9-2. Serial I/O Port Timing 9.4 SSI Registers The SSI has three registers: control, status, and data. 9.4.1 SSI Control Register This register is located at address $001E and contains seven bits. A reset clears all of these bits, except bit 3 which is set. Writes to this register during a transfer should be avoided, with the exception of clearing the SE bit to disable the SSI. In addition, the clock polarity, rate, data format and master/slave selection should not be changed while the SSI is enabled (SE = 1) or General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) SSI Registers being enabled. Always disable the SSI first, by clearing the SE bit, before altering these control bits within the SSI control register (SCR). Address: $001E Bit 7 Read: SIE Write: Reset: 0 0 0 0 1 0 0 0 SE LSBF MSTR CPOL T/R SR1 SR0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... SIE -- SSI Interrupt Enable This bit determines whether an interrupt request should be generated when a transfer is complete. When set, an interrupt request is made if the CPU is in the run or wait mode of operation and status flag bit SF is set. When cleared, no interrupt requests are made by the SSI. SE -- SSI Enable When set, this bit enables the SSI, makes PD5 the SCK pin, and makes PD4 the SDIO pin. When SE is cleared, any transmission in progress is aborted, the bit counter is reset, and pins SCK and SDIO revert to being PD5 and PD4. LSBF -- Least Significant Bit (LSB)First When set, data is sent and received in a least significant bit (LSB) first format. When cleared, data is sent and received in a most significant bit (MSB) first format. MSTR -- Master Mode When set, this bit configures the SSI to the master mode. This means that the transmission is initiated by a write to the data register and the SCK pin becomes an output providing a synchronous data clock at a rate determined by the SR bits. MC68HC05CT4 -- Rev. 2.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT Figure 9-3. SSI Control Register (SCR) REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED When cleared, this bit configures the SSI to the slave mode and aborts any transmission in progress. Transfers are initiated by an external master, which should supply the clock to the SCK pin. CPOL -- Clock Polarity The clock polarity bit controls the state of the SCK pin between transmissions. When this bit is set, pin SCK is high between transmissions. When this bit is cleared, pin SCK is low between transmissions. In both cases the data is latched on the rising edge of SCK for serial input and is valid on the rising edge of SCK for serial output. A reset sets this bit. Freescale Semiconductor, Inc... AGREEMENT NOTE: If the SSI is used as a slave, the SCK input pin must be active before enabling the SSI. For example, if CPOL = 0, SCK must be low; if CPOL = 1, SCK must be high. T/R -- Transmit/Receive This bit must be set to allow data to be driven on the SDIO pin (transmitting). It must be cleared to disable the SDIO drivers when receiving data. It is cleared by a reset. SR1 and SR0 -- SSI Rate These bits determine the frequency of SCK when in master mode (MSTR = 1). They have no effect in slave mode (MSTR = 0). Table 9-1. SSI Rates SR1 and SR0 00 01 10 11 NON-DISCLOSURE SCK Rates (Hz) at fosc Frequency 32 kHz 64 kHz 128 kHz 256 kHz General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) SSI Registers 9.4.2 SSI Status Register This register is located at address $001C and contains two bits. Reset clears both of these bits. Address: $001C Bit 7 Read: Write: SF 6 DCOL 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Reset: 0 0 0 Figure 9-4. SSI Status Register (SSR) SF -- SSI Flag This bit is set upon occurrence of the last rising clock edge and indicates that a data transfer has taken place. If MSTR = 0 and SIE = 0, this bit has no effect on any further transmissions and can be ignored without problem. However, the SF flag must be clear to write the data register, or if SIE = 1 to clear the interrupt. If MSTR = 1, the SF flag must be cleared between transfers. The SF flag can be cleared three different ways: (1) by reading the SSR with SF set, followed by a read or write of the serial data register, (2) by a system reset, or, (3) by disabling the SSI. If the SF flag is cleared before the last edge of the next byte, it will be set again. DCOL -- Data Collision This is a read-only status bit, which indicates that an invalid access to the data register was made. An invalid access can be one of the following conditions: * * An access of the SDR register in the middle of a transfer (after the first falling edge of SCK and before SF is set) An access of the SDR register made before an access of the SSR register (after SF is set) DCOL is cleared by reading the status register with SF set followed by a read or write of the data register. A reset also clears this bit. MC68HC05CT4 -- Rev. 2.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED 9.4.3 SSI Data Register This register is located at address $001D and is both the transmit and receive data register. This system is not double buffered, but any writes to this register during transfers are masked and will not destroy the previous contents. The SDR can be read at any time, but, if a transfer is in progress the results may be ambiguous. The contents of this register could be altered whenever the CPOL bit is altered. This register should be written to only upon completion of a transfer, after the SF flag has been cleared. Otherwise, the new data will not be stored. For an SSI configured as a master, to initiate a transfer, the data register write must occur after the SSI is enabled. Address: $001D Bit 7 Read: Write: Reset: U U U U U U U U 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... AGREEMENT Figure 9-5. SSI Data Register (SDR) NON-DISCLOSURE 9.5 Operation During Wait Mode The CPU clock halts during wait mode, but the SSI remains active. If interrupts are enabled, an SSI interrupt will cause the processor to exit wait mode. 9.6 Operation During Stop Mode In stop mode, the SSI halts operation. The SDIO and SCK pins will maintain their states. If the SSI is nearing completion of a transfer when the stop mode is entered, it might be possible for the SSI to generate an interrupt request and thus cause the processor immediately to exit stop mode. To prevent General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) SSI Power Supply Source this occurrence, the programmer should ensure that all transfers are complete before entering the stop mode. If the SSI is configured to slave mode, further care should be taken in entering stop mode. The SCK pin will still accept a clock from an external master, allowing potentially unwanted transfers to take place and power consumption to be increased. The SSI will not generate interrupt requests in this situation but, on exiting stop mode through some other means, the SF flag may be found to be set and an interrupt request will be generated if SIE is also set at this point. Freescale Semiconductor, Inc... To avoid these potential problems, it is safer to disable the SSI completely (SE = 0) before entering stop mode. The synchronous serial interface (SSI) is a 2-wire master/slave system including serial clock (SCK) and serial data input/output (SDIO). When operating as a master device, the serial clock speed is selectable between four rates. 9.7 SSI Power Supply Source The power supplied to the SSI is VDD and VSS, thus keeping the VDD2 and VSS2 free for the noise susceptible modules. MC68HC05CT4 -- Rev. 2.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED NON-DISCLOSURE General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 10. Core Timer 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .81 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .83 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .84 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Core Timer Power Supply Source . . . . . . . . . . . . . . . . . . . . . .84 Freescale Semiconductor, Inc... 10.3 10.4 10.5 10.6 10.7 10.2 Introduction The core timer for this device is a 12-stage multifunctional ripple counter. Features include timer overflow, power-on reset (POR), real-time interrupt (RTI), and COP watchdog timer. As seen in Figure 10-1, the internal peripheral clock is divided by four, and then drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the core timer counter register (CTCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt rate of the internal peripheral clock(E)/1024. This point is then followed by three more stages, with the resulting clock (E/16384) driving the realtime interrupt circuit (RTI). The RTI circuit consists of three divider stages with a one-of-four selector. The output of the RTI circuit is further divided by eight to drive the mask optional COP watchdog timer circuit. The RTI rate selector bits and the RTI and CTOF enable bits and flags are located in the timer control and status register at location $08. MC68HC05CT4 -- Rev. 2.0 Core Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Core Timer REQUIRED INTERNAL BUS 8 8 CTCR $09 CORE TIMER COUNTER REGISTER (CTCR) INTERNAL PERIPHERAL CLOCK (E) E/22 COP CLEAR E/210 DIV /4 E / 212 POR Freescale Semiconductor, Inc... AGREEMENT 5-BIT COUNTER E / 217 E / 216 E / 215 E / 214 TCBP RTI SELECT CIRCUIT OVERFLOW DETECT CIRCUIT RTIOUT CTCSR CTOF RTIF TOFE RTIE TOFC RTFC RT1 RT0 $08 TIMER CONTROL & STATUS REGISTER NON-DISCLOSURE INTERRUPT CIRCUIT COP WATCHDOG TIMER (/ 8) 23 TO INTERRUPT LOGIC TO RESET LOGIC Figure 10-1. Core Timer Block Diagram General Release Specification Core Timer For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Core Timer Core Timer Control and Status Register 10.3 Core Timer Control and Status Register The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. Figure 10-2 shows the value of each bit in the CTCSR when coming out of reset. Address $0008 Bit 7 Read: CTOF 6 RTIF TOFE Write: Reset: 0 0 0 0 RTIE TOFC 0 RTRC 0 1 1 5 4 3 0 2 0 1 RT1 Bit 0 RT0 Freescale Semiconductor, Inc... = Unimplemented Figure 10-2. Core Timer Control and Status Register (CTCSR) CTOF -- Core Timer Overflow CTOF is a read-only status bit set when the 8-bit ripple counter rolls over from $FF to $00. Clearing CTOF is done by writing a logic 1 to TOFC. Writing to CTOF has no effect. Reset clears CTOF. RTIF -- Real Time Interrupt Flag The real-time interrupt circuit consists of a 3-stage divider and a oneof-four selector. The clock frequency that drives the RTI circuit is E/2**14 (or E/16,384) with three additional divider stages, giving a maximum interrupt period of 64 milliseconds at a bus rate of 2.048 MHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (one-of-four selection) stage goes active. Clearing RTIF is done by writing a logic 1 to RTFC. Writing to RTIF has no effect. Reset clears RTIF. TOFE -- Timer Overflow Enable When this bit is set, a CPU interrupt request is generated when the CTOF bit is set. Reset clears this bit. RTIE -- Real-Time Interrupt Enable When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset clears this bit. MC68HC05CT4 -- Rev. 2.0 Core Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Core Timer REQUIRED TOFC -- Timer Overflow Flag Clear When a logic 1 is written to this bit, CTOF is cleared. Writing a logic 0 has no effect on the CTOF bit. This bit always reads as zero. RTFC -- Real-Time Interrupt Flag Clear When a logic 1 is written to this bit, RTIF is cleared. Writing a logic 0 has no effect on the RTIF bit. This bit always reads as zero. RT1 and RT0 -- Real-Time Interrupt Rate Select Freescale Semiconductor, Inc... AGREEMENT These two bits select one of four taps from the real-time interrupt circuit. See Table 10-1. Reset sets these two bits, which selects the slowest periodic rate and gives the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the timeout period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing RTI taps. Table 10-1. RTI and COP Rates at 2.048 MHz RTI Rate 2.048 MHz 8 ms 16 ms 32 ms 64 ms RT1 and RT0 00 01 10 11 Minimum COP Rates 2.048 MHz (217-214)/E (218-215)/E (219-216)/E (220-217)/E 56 ms 112 ms 224 ms 448 ms NON-DISCLOSURE 214/E 215/E 216/E 217/E General Release Specification Core Timer For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Core Timer Core Timer Counter Register 10.4 Core Timer Counter Register The timer counter register is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked by the CPU clock (E/4) and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location, thereby simulating a 16-bit (or more) counter. Address $0009 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 1 1 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 Bit 0 D0 Freescale Semiconductor, Inc... = Unimplemented Figure 10-3. Core Counter Register (CTCR) The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 cycles, the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer starts counting up from zero and normal device operation begins. When RESET is asserted any time during operation (other than POR), the counter chain is cleared. MC68HC05CT4 -- Rev. 2.0 Core Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Core Timer REQUIRED 10.5 Computer Operating Properly (COP) Reset The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 10-1. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP timeout or clearing the COP is accomplished by writing a logic 0 to bit 0 of address $1FF0. When the COP is cleared, only the final divide-by-eight stage (output of the RTI) is cleared. If the COP watchdog timer is allowed to time out, an internal reset is generated to reset the MCU. In addition, the RESET pin is pulled low for a minimum of one E-clock cycle for emulation purposes. The COP remains enabled after execution of the WAIT instruction and all associated operations apply. If the STOP instruction is disabled, execution of STOP instruction causes the CPU to execute a NOP instruction. In addition, the COP is prohibited from being held in RESET. This prevents a device lock-up condition. This COP's objective is to make it impossible for this device to become stuck or locked-up and to be sure the COP is able to rescue the part from any situation where it might entrap itself in abnormal or unintended behavior. This function is a mask option. NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT 10.6 Timer During Wait Mode The CPU clock halts during wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. The COP is always enabled while in user mode. 10.7 Core Timer Power Supply Source The core timer is supplied by VDD and VSS. VDD2 and VSS2 are not needed here because this module is not susceptible to supply noise. General Release Specification Core Timer For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 11. Dual Phase-Locked Loop (PLL) 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Freescale Semiconductor, Inc... 11.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.3.1 Dual Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.3.2 12-Bit Reference Counter Modulus Register. . . . . . . . . . . .89 11.3.3 16-Bit Transmit Counter Modulus Register . . . . . . . . . . . . .90 11.3.4 16-Bit Receive Counter Modulus Register . . . . . . . . . . . . .91 11.4 PLL Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 MC68HC05CT4 -- Rev. 2.0 Dual Phase-Locked Loop (PLL) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Dual Phase-Locked Loop (PLL) REQUIRED 11.2 Introduction This dual PLL is similar to that of the MC145162 60-MHz universal programmable dual PLL frequency synthesizer. It is especially designed for CT-1 cordless phone applications. The PLL features fully programmable 16-bit receive, 16-bit transmit, and 12-bit reference ripple down counters. It also has two independent phase detectors for transmit and receive loops. The FinTx and FinRx signals are input to the PLL transmit and receive counters, respectively. They are typically driven by the loop VCO and AC-coupled. The minimum input signal level is 200 mVp-p @ 60.0 MHz. Freescale Semiconductor, Inc... AGREEMENT OSC (10.24 MHz) 12-BIT PROGRAMMABLE REFERENCE COUNTER /4 / 25 /5 PLS1 PLS0 TX PHASE DETECTOR TxPDOUT NON-DISCLOSURE MCU BUS FinT 16-BIT PROGRAMMABLE TX COUNTER RX PHASE DETECTOR RxPDOUT FinR 16-BIT PROGRAMMABLE RX COUNTER Figure 11-1. Dual PLL Block Diagram General Release Specification Dual Phase-Locked Loop (PLL) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Dual Phase-Locked Loop (PLL) Registers 11.3 Registers The PLL has one 12-bit programmable counter, two 16-bit programmable counters, and one control register. 11.3.1 Dual Control Register The PLLCR contains bits that affect the operation of the PLL. Freescale Semiconductor, Inc... Bit 7 Read: Write: Reset: 0 6 TLOCK 5 RLOCK 4 REFON 3 TXON 0 2 RXON 0 1 PLS1 0 Bit 0 PLS0 0 0 0 0 = Unimplemented Figure 11-2. Dual PLL Control Register PLS1 and PLS0 -- PLL Reference Counter Select These bits select between the PLL reference counter MUX outputs. This output signal then drives the phase detectors. Table 11-1. PLL Reference Counter Select PLS1 and PLS0 00 01 10 11 PLL Reference Counter Output /12-Bit Counter /4 After 12-Bit Counter /5 After 12-Bit Counter /25 After 12-Bit Counter RXON -- RX Counter Enable When set, this bit enables the PLL receive counter. When clear, it stops the receive counter in a reset state to save power. RXON also shuts off the associated phase detector and holds it in three-state. Initializing the receive counter before it is enabled is recommended. MC68HC05CT4 -- Rev. 2.0 Dual Phase-Locked Loop (PLL) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT Address: $000A REQUIRED Freescale Semiconductor, Inc. Dual Phase-Locked Loop (PLL) REQUIRED TXON -- TX Counter Enable When set, this bit enables the PLL transmit counter. When clear, it stops the counter in a reset state to save power. TXON also shuts off the associated phase detector and holds it in threestate. Initializing the transmit counter before it is enabled is recommended. REFON -- Reference Counter Enable When set, this bit enables the PLL reference counter. When clear, REFON stops the reference counter in a reset state to save power. Initializing the reference counter before it is enabled is recommended. RLOCK -- Receive Lock Detect This bit is read only and is not latched. When set, this bit is a real-time indication of an active correction pulse from the phase detect in progress. When clear, no correction is made and the output from the phase detect is three-stated. Using multiple reads at known intervals will allow the user to filter and judge a LOCK condition. TLOCK -- Transmit Lock Detect This bit is read only and is not latched.When set, this bit is a real-time indication of an active correction pulse from the phase detect in progress. When clear, no correction is made and the output from the phase detect is three-stated. Using multiple reads at known intervals will allow the user to filter and judge a LOCK condition. NON-DISCLOSURE General Release Specification Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Dual Phase-Locked Loop (PLL) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Dual Phase-Locked Loop (PLL) Registers 11.3.2 12-Bit Reference Counter Modulus Register This 2-byte register holds the count for the 12-bit reference counter. The reference counter is shut off and held in reset when the REFON bit is cleared. For proper operation, this register must not be loaded with a value less than $000F. Address: $000B Bit 7 6 5 4 3 2 1 Bit 0 PLLRC8 0 Freescale Semiconductor, Inc... PLLRC11 PLLRC10 PLLRC9 Write: Reset: 0 0 0 0 0 0 0 Address: $000C Bit 7 6 PLLRC6 0 5 PLLRC5 0 4 PLLRC4 0 3 PLLRC3 0 2 PLLRC2 0 1 PLLRC1 0 Bit 0 PLLRC0 0 Read: PLLRC7 Write: Reset: 0 = Unimplemented Figure 11-3. 12-Bit Reference Counter (PLLRC) NOTE: Bit 4 to bit 7 of $000B are not used but they are physically present. The user may use these four bits for scratch memory. MC68HC05CT4 -- Rev. 2.0 Dual Phase-Locked Loop (PLL) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT Read: REQUIRED Freescale Semiconductor, Inc. Dual Phase-Locked Loop (PLL) REQUIRED 11.3.3 16-Bit Transmit Counter Modulus Register This 2-byte register holds the count for the 16-bit transmit counter. The transmit counter is shut off and held in reset when the TXON bit is cleared. For proper operation, this register must not be loaded with a value less than $000F. Address: $000D Bit 7 6 5 4 3 2 1 PLLTX9 0 Bit 0 PLLTX8 0 Freescale Semiconductor, Inc... AGREEMENT Read: PLLTX15 PLLTX14 PLLTX13 PLLTX12 PLLTX11 PLLTX10 Write: Reset: 0 0 0 0 0 0 Address: $000E Bit 7 6 PLLTX6 0 5 PLLTX5 0 4 PLLTX4 0 3 PLLTX3 0 2 PLLTX2 0 1 PLLTX1 0 Bit 0 PLLTX0 0 Read: PLLTX7 Write: Reset: 0 NON-DISCLOSURE Figure 11-4. 16-Bit Transmit Counter (PLLTX) General Release Specification Dual Phase-Locked Loop (PLL) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Dual Phase-Locked Loop (PLL) Registers 11.3.4 16-Bit Receive Counter Modulus Register This 2-byte register holds the count for the 16-bit receive counter. The receive counter is shut off and held in reset when the RXON bit is cleared. For proper operation, this register must not be loaded with a value less than $000F. Address: $000F Bit 7 6 5 4 3 2 1 PLLRX9 0 Bit 0 PLLRX8 0 Freescale Semiconductor, Inc... PLLRX15 PLLRX14 PLLRX13 PLLRX12 PLLRX11 PLLRX10 Write: Reset: 0 0 0 0 0 0 Address: $0010 Bit 7 6 PLLRX6 0 5 PLLRX5 0 4 PLLRX4 0 3 PLLRX3 0 2 PLLRX2 0 1 PLLRX1 0 Bit 0 PLLRX0 0 Read: PLLRX7 Write: Reset: 0 Figure 11-5. 16-Bit Receive Counter (PLLRX) The modulus registers mentioned above have specific read/write logic. When the user updates the contents of the modulus registers, the MSB must be written first and is temporarily stored in a temporary buffer. This inhibits the transfer of data from this level to the next level, which is the modulus register. When the LSB is written, all 12 or 16 bits (data from the temporary buffer and the MCU internal bus) are transferred to the modulus register simultaneously. This prevents the loading of bad data from the modulus register. A read of the data registers is the reverse of a write operation. A read of the LSB buffers the MSB. A subsequent read of the MSB reflects this buffered value. Since only one temporary buffer exists, two sequential MSB writes of different registers will result in only the last data value stored in the temporary buffer. The first value will be lost. MC68HC05CT4 -- Rev. 2.0 Dual Phase-Locked Loop (PLL) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT Read: REQUIRED Freescale Semiconductor, Inc. Dual Phase-Locked Loop (PLL) REQUIRED MCU INTERNAL BUS MSB LSB MODULUS COUNTER Freescale Semiconductor, Inc... AGREEMENT NOTE: Not available for the 12-bit reference counter. Figure 11-6. Counter Structure Block Diagram 11.4 PLL Power Supply Source The PLL is supplied by VDD, VDD2, VSS, and VSS2. VDD and VSS are reserved for the digital circuitry, while VDD2 and VSS2 are reserved for the analog circuitry such as the phase detect and the amplifiers which are sensitive to supply noise. NON-DISCLOSURE General Release Specification Dual Phase-Locked Loop (PLL) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 12. Pulse Width Modulator (PWM) 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 PWM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 PWM During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PWM During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PWM During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PWM Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Freescale Semiconductor, Inc... 12.3 12.4 12.5 12.6 12.7 12.8 MC68HC05CT4 -- Rev. 2.0 Pulse Width Modulator (PWM) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) REQUIRED 12.2 Introduction The pulse width modulator (PWM) system has one 6-bit channel to enable the correct pulse output. The PWM has a fixed frequency of E/64, where E is the internal bus frequency. For a PWM output frequency of 32 kHz, E must be 2.048 MHz. This corresponds to a 10.24-MHz crystal with the divide-by-five crystal option. AGREEMENT Freescale Semiconductor, Inc... BUFFER HC05 DATA BUS MODULUS & COMPARATOR PWM PIN LOGIC PC7/PWM E 6-BIT COUNTER MISCELLANEOUS CONTROL REGISTER NON-DISCLOSURE Figure 12-1. PWM Block Diagram General Release Specification Pulse Width Modulator (PWM) For More Information On This Product, Go to: www.freescale.com PWME MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Functional Description 12.3 Functional Description A $00 in the PWM data register yields an off output (0%), but a $3F yields a duty of 63/64 (98.4%). When not in use, the PWM system can be shut off to save power by clearing the PWME bit in MISCR. Writes to the PWM data register can be performed at any time without affecting the current PWM output signal. Updates on the PWM output occur at the end of the PWM period (E x 64). At this time, the new value is loaded into the PWM data register. If a write to the registers is performed while the PWM is disabled, data is transferred directly to the PWM register. A read of the data register reads the active count in progress, not the buffered value. After the PWM is enabled (PWM = 1) the PWM output remains low for one E cycle. This allows synchronization and will not occur again until the next time the PWM is enabled. Freescale Semiconductor, Inc... 64 x E 10 3F 20 0 Figure 12-2. PWM Waveforms MC68HC05CT4 -- Rev. 2.0 Pulse Width Modulator (PWM) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) REQUIRED 12.4 PWM Data Register One PWM data register (PWMDR), located at $0020, is associated with the PWM system. This 8-bit data register holds the duty cycle for the PWM output; however, only six of these bits are used. PWMDR can be written to and read at any time. Writes to the PWMDR are buffered and are not transferred to the active register until the end of the PWM cycle during which the write was executed. Address: $0020 Bit 7 Read: 0 Write: Reset: Unaffected by Reset 0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... AGREEMENT Figure 12-3. PWM Data Register (PWMDR) Upon RESET the user should write to the data register prior to enabling the PWM system (for example, prior to setting the PWME bit in the miscellaneous control register). This avoids an erroneous duty cycle from being driven. PWME -- Miscellaneous Control Register PWM Enable Bit When set, this bit enables the PWM subsystem. Its main function is to allow the user to save power when not using the PWM. When enabled, the clocks are active to the module. When clear, this bit shuts off the clocks to the module and relinquishes control of PC7 to the port C logic (the PC7 pullup option should not be selected if the PWM is used). Reset clears this bit. This bit is located in the miscellaneous control register found in Section 13. Comparators. NON-DISCLOSURE General Release Specification Pulse Width Modulator (PWM) For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) PWM During Wait Mode 12.5 PWM During Wait Mode The PWM continues normal operation during wait mode. To decrease power consumption during WAIT, it is recommended that the PWME bit in the miscellaneous control register be cleared if the PWM D/A converter is not being used. 12.6 PWM During Stop Mode Freescale Semiconductor, Inc... 12.7 PWM During Reset Upon reset the PWME bit is cleared. In effect, this disables the PWM system and configures the PC7/PWM pin as a high impedance port C input pin. The user should write to the data register prior to enabling the PWM system (for instance, prior to setting PWME). This avoids an erroneous duty cycle from being driven. 12.8 PWM Power Supply Source The PWM is supplied by VDD and VSS, due to the noise generated by the digital circuitry, since this module is not affected by supply noise. MC68HC05CT4 -- Rev. 2.0 Pulse Width Modulator (PWM) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT In stop mode, the oscillator is stopped, causing the PWM to cease function. Any signal in process is halted in whatever phase the signal happens to be in. Disabling the PWM before executing the STOP instruction is recommended. REQUIRED Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) REQUIRED NON-DISCLOSURE General Release Specification Pulse Width Modulator (PWM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 13. Comparators 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Comparator Control/Status Register. . . . . . . . . . . . . . . . . . . .101 Reading Comparator Outputs. . . . . . . . . . . . . . . . . . . . . . . . .103 Comparator During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . .103 Comparator During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . .103 Comparator Power Supply Source . . . . . . . . . . . . . . . . . . . . .103 Freescale Semiconductor, Inc... 13.3 13.4 13.5 13.6 13.7 13.2 Introduction Port D shares its pins with CMP3+/PD0, CMP1-/PD1 and CMP12+/PD2, CMP2-/PD3 of the comparators. The output of the comparators is a status bit internal to the MCU. This circuitry is used for the comparison of analog signals, with a digital output. The comparator circuitry may be powered up by setting the CEN1, CEN2, and the CEN3 bits in the comparator control/status register. This register is located at $0022 and is cleared by reset. The state of the comparator output bit upon RESET is logic 0. For further electrical information see Section 16. Electrical Specifications. MC68HC05CT4 -- Rev. 2.0 Comparators For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Comparators REQUIRED + CMP1 - PD1/ CMP1- VOLTAGE COMPARATOR 1 CEN1 PORT D Freescale Semiconductor, Inc... AGREEMENT CEN2 VOLTAGE COMPARATOR 2 PD3/ CMP2- - CMP2 PD2/ CMP12+ + CEN3 VOLTAGE COMPARATOR 3 INTERNAL REF - PD0/ CMP3+ CM3IE CMP3 CMP3 INT NON-DISCLOSURE + Figure 13-1. Comparator Block Diagram General Release Specification Comparators For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Comparators Comparator Control/Status Register 13.3 Comparator Control/Status Register Address: $0022 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 CMP3 6 CMP2 5 CMP1 CM3IE 0 CEN3 CEN2 CEN1 4 3 2 1 Bit 0 = Unimplemented Freescale Semiconductor, Inc... Figure 13-2. Comparator Control/Status Register (CMPCSR) CMP3 -- Comparator 3 Output This bit is implemented in two ways: as a real-time comparator output or as a latched interrupt source. The state of CM3IE determines which implementation is selected. CM3IE = 0 (nonlatched mode) -- This status bit is cleared only by two means: 1. Clearing CM3IE while the voltage at CMP3+ is less than CMP3- 2. By an external reset CM3IE = 1 (latched mode) -- This latched status bit is set when the voltage at CMP3+ (PD0) is larger than that of CMP3- (internal voltage reference ~ 2 VDD/3). An interrupt is then initiated ($1FFA-$1FFB). CMP2 -- Comparator 2 Output This status bit is set when the voltage at CMP12+ is larger than that of CMP2-, otherwise, it is cleared. Reset clears this bit because the comparator is disabled. CMP1 -- Comparator 1 Output This status bit is set when the voltage at CMP12+ is larger than that of CMP1-, otherwise, it is cleared. Reset clears this bit because the comparator is disabled. MC68HC05CT4 -- Rev. 2.0 Comparators For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Comparators REQUIRED CM3IE -- Comparator 3 Interrupt Enable This control bit, when set, allows CMP3 to generate an interrupt when it goes high. CEN3 -- Comparator 3 Enable This control bit, when set, powers up the voltage comparator 3 on PD0. The user must set this bit to allow any functionality of the comparator. After enabling the comparator, the user should delay for tCEN before reading the state of the output or enabling the interrupt. Reset clears this bit. PD0 remains under control of its DDR bit to enable the user to drive CMP3+ to a desired level. When CEN3 is cleared, the comparator is disabled and consumes negligible power. CEN2 -- Comparator 2 Enable This control bit, when set, powers up the voltage comparator 2 on PD2 and PD3. The user must set this bit to allow any functionality of the comparator. After enabling the comparator, the user should delay for tCEN before reading the state of the output. Reset clears this bit. PD2 and PD3 remain under control of their DDR bits to enable the user to drive CMP2- and CMP12+ to desired levels. When CEN2 is cleared, the comparator is disabled and consumes negligible power. CEN1 -- Comparator 1 Enable This control bit, when set, powers up voltage comparator 1 on PD1 and PD2. The user must set this bit to allow any functionality of the comparator. After enabling the comparator, the user should delay for tCEN before reading the state of the output. Reset clears this bit. PD1 and PD2 remain under control of their DDR bits to enable the user to drive CMP1- and CMP12+ to desired levels. When CEN1 is cleared, the comparator is disabled and consumes negligible power. NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT General Release Specification Comparators For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Comparators Reading Comparator Outputs 13.4 Reading Comparator Outputs The state of each comparator output bit is internally readable from the CMPCSR. 13.5 Comparator During Wait Mode The comparator operates normally in wait mode. If the user wishes to save power during the wait mode, the CEN1, CEN2, and CEN3 bits should be cleared before the WAIT instruction. Freescale Semiconductor, Inc... 13.6 Comparator During Stop Mode Stop mode does not affect the comparator circuit. If the user needs to save power, the CEN1, CEN2, and CEN3 bits should be cleared before the STOP instruction. 13.7 Comparator Power Supply Source The comparators are supplied by VDD2 and VSS2. These power lines are reserved for noise-susceptible circuitry, such as the circuitry found in the comparators. MC68HC05CT4 -- Rev. 2.0 Comparators For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Comparators REQUIRED NON-DISCLOSURE General Release Specification Comparators For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 14. Miscellaneous Register 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Miscellaneous Control Register . . . . . . . . . . . . . . . . . . . . . . .105 Miscellaneous Register Power Supply Source . . . . . . . . . . . .106 Freescale Semiconductor, Inc... 14.3 14.4 14.2 Introduction The miscellaneous register exists to hold various system control bits. It is located at address $0021. 14.3 Miscellaneous Control Register Address: $0021 Bit 7 Read: 0 Write: Reset: 0 0 0 0 0 0 0 0 0 0 0 SPEED COE PWME 0 6 5 4 3 2 1 Bit 0 Figure 14-1. Miscellaneous Control Register (MISCR) SPEED -- CPU Speed Select This control bit, when set, selects an additional divide-by-eight after the already divide-by-five from the oscillator clock to the internal bus clock. This makes the internal CPU clock a divide-by-40 from the oscillator input. When clear, the internal bus clock is a divide-by-five from the oscillator input. Reset clears this bit. MC68HC05CT4 -- Rev. 2.0 Miscellaneous Register For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Miscellaneous Register REQUIRED COE -- 16-Bit Timer Output Compare Enable This control bit, when set, enables the 16-bit output compare function to come out on PD6/TCMP. When clear, PD6 returns to a generalpurpose I/O pin. PWME -- PWM Enable This control bit, when set, enables the PWM function to come out on PC7/PWM. When clear, PC7 returns to a general-purpose I/O pin. Freescale Semiconductor, Inc... AGREEMENT 14.4 Miscellaneous Register Power Supply Source The miscellaneous control register is supplied by VDD and VSS. VDD2 and VSS2 are reserved for noise-susceptible circuitry. NON-DISCLOSURE General Release Specification Miscellaneous Register For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 15. Instruction Set 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Freescale Semiconductor, Inc... 15.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 15.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 15.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 15.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 15.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 15.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 15.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 15.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 15.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 15.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 15.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .112 15.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .113 15.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .114 15.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .116 15.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 15.5 15.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 15.2 Introduction The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator. Freescale Semiconductor, Inc... AGREEMENT 15.3 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative NON-DISCLOSURE General Release Specification MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Instruction Set Addressing Modes 15.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 15.3.2 Immediate Freescale Semiconductor, Inc... Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 15.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. 15.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 15.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. Freescale Semiconductor, Inc... AGREEMENT 15.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. NON-DISCLOSURE 15.3.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Instruction Set Instruction Types 15.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. Freescale Semiconductor, Inc... 15.4 Instruction Types The MCU instructions fall into the following five categories: * * * * * Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT When using the Motorola assembler, the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch. REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 15.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 15-1. Register/Memory Instructions Instruction Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB AGREEMENT Freescale Semiconductor, Inc... Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator NON-DISCLOSURE General Release Specification MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Instruction Set Instruction Types 15.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. Table 15-2. Read-Modify-Write Instructions Instruction Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2) Freescale Semiconductor, Inc... Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 15.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. NON-DISCLOSURE General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Instruction Set Instruction Types Table 15-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL Freescale Semiconductor, Inc... Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine BRCLR BRN BRSET BSR JMP JSR MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE BRA AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 15.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 15-4. Bit Manipulation Instructions Instruction Mnemonic BCLR BRCLR BRSET BSET AGREEMENT Freescale Semiconductor, Inc... Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set NON-DISCLOSURE General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Instruction Set Instruction Types 15.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 15-5. Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT Freescale Semiconductor, Inc... No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 15.5 Instruction Set Summary Table 15-6. Instruction Set Summary Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel Operation Description H I NZC Add with Carry A (A) + (M) + (C) -- Freescale Semiconductor, Inc... AGREEMENT IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL ii A9 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 ii A4 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3 Add without Carry A (A) + (M) -- Logical AND A (A) (M) ---- -- Arithmetic Shift Left (Same as LSL) C b7 b0 0 ---- NON-DISCLOSURE ff dd Arithmetic Shift Right b7 b0 C ---- ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr Branch if Carry Bit Clear PC (PC) + 2 + rel ? C = 0 ---------- BCLR n opr Clear Bit n Mn 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- ---------- ---------- REL REL REL REL REL REL BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C Z = 0 PC (PC) + 2 + rel ? C = 0 General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Cycles Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. Instruction Set Instruction Set Summary Table 15-6. Instruction Set Summary (Continued) Opcode Source Form BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operation Branch if IRQ Pin High Branch if IRQ Pin Low Description PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 H I NZC ---------- ---------- REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL 2F 2E A5 B5 C5 D5 E5 F5 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr ii dd hh ll ee ff ff rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd Bit Test Accumulator with Memory Byte (A) (M) ---- -- Freescale Semiconductor, Inc... Cycles 3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 2 2 Effect on CCR Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? C Z = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1 ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- BRCLR n opr rel Branch if Bit n Clear PC (PC) + 2 + rel ? Mn = 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- REL BRN rel Branch Never PC (PC) + 2 + rel ? 1 = 0 BRSET n opr rel Branch if Bit n Set PC (PC) + 2 + rel ? Mn = 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) BSET n opr Set Bit n Mn 1 BSR rel Branch to Subroutine PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0 ---------- REL AD rr CLC CLI Clear Carry Bit Clear Interrupt Mask -------- 0 -- 0 ------ INH INH 98 9A MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Operand Address Mode Freescale Semiconductor, Inc. Instruction Set REQUIRED Table 15-6. Instruction Set Summary (Continued) Opcode Source Form CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Operation Description M $00 A $00 X $00 M $00 M $00 H I NZC Clear Byte ---- 0 1 -- DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX 3F 4F 5F 6F 7F dd ff Freescale Semiconductor, Inc... AGREEMENT Compare Accumulator with Memory Byte (A) - (M) ---- ii A1 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5 Complement Byte (One's Complement) M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M) ---- 1 ff Compare Index Register with Memory Byte (X) - (M) ---- ii A3 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5 NON-DISCLOSURE Decrement Byte M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 ---- -- ff EXCLUSIVE OR Accumulator with Memory Byte A (A) (M) ---- -- ii A8 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5 Increment Byte M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 ---- -- ff Unconditional Jump PC Jump Address ---------- BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2 General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Cycles 5 3 3 6 5 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. Instruction Set Instruction Set Summary Table 15-6. Instruction Set Summary (Continued) Opcode Source Form JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X Operation Description H I NZC PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address Jump to Subroutine ---------- DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 ii A6 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D AA BA CA DA EA FA 39 49 59 69 79 ii dd hh ll ee ff ff dd dd dd 5 3 3 6 5 5 3 3 6 5 11 5 3 3 6 5 2 2 3 4 5 4 3 5 3 3 6 5 Freescale Semiconductor, Inc... Load Index Register with Memory Byte X (M) ---- -- Logical Shift Left (Same as ASL) C b7 b0 0 ---- ff dd Logical Shift Right 0 b7 b0 C ---- 0 Unsigned Multiply X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) 0 ------ 0 Negate Byte (Two's Complement) ---- ff No Operation ---------- Logical OR Accumulator with Memory A (A) (M) ---- -- Rotate Byte Left through Carry Bit C b7 b0 ---- ff MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE ff AGREEMENT Load Accumulator with Memory Byte A (M) ---- -- Cycles Effect on CCR REQUIRED Operand Address Mode Freescale Semiconductor, Inc. Instruction Set REQUIRED Table 15-6. Instruction Set Summary (Continued) Opcode Source Form ROR opr RORA RORX ROR opr,X ROR ,X RSP Operation Description H I NZC Rotate Byte Right through Carry Bit b7 b0 C ---- DIR INH INH IX1 IX INH 36 46 56 66 76 9C dd ff Reset Stack Pointer SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) ---------- Freescale Semiconductor, Inc... AGREEMENT RTI Return from Interrupt INH 80 RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Return from Subroutine ---------- INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX 81 Subtract Memory Byte and Carry Bit from Accumulator A (A) - (M) - (C) ---- ii A2 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B B7 C7 D7 E7 F7 8E BF CF DF EF FF dd hh ll ee ff ff dd hh ll ee ff ff 2 2 4 5 6 5 4 2 4 5 6 5 4 Set Carry Bit Set Interrupt Mask C1 I1 -------- 1 -- 1 ------ NON-DISCLOSURE Store Accumulator in Memory M (A) ---- -- Stop Oscillator and Enable IRQ Pin -- 0 ------ Store Index Register In Memory M (X) ---- -- Subtract Memory Byte from Accumulator A (A) - (M) ---- ii A0 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3 SWI Software Interrupt PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ---------- INH 83 10 TAX Transfer Accumulator to Index Register INH 97 General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Cycles 5 3 3 6 5 2 9 6 2 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. Instruction Set Opcode Map Table 15-6. Instruction Set Summary (Continued) Opcode Source Form TST opr TSTA TSTX TST opr,X TST ,X TXA Operation Description H I NZC Test Memory Byte for Negative or Zero (M) - $00 ---- -- DIR INH INH IX1 IX INH INH 3D 4D 5D 6D 7D 9F 8F dd ff Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit A (X) ---------- -- 0------ Freescale Semiconductor, Inc... WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n 2 Cycles 4 3 3 5 4 2 Effect on CCR 15.6 Opcode Map See Table 15-7. MC68HC05CT4 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : -- Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected AGREEMENT REQUIRED Operand Address Mode N O N - D I S C LFreescale Semiconductor, IN T OSURE A G R E E M E nc... R E Q U I R E D Table 15-7. Opcode Map Branch Register/Memory IMM IX F 3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA 2 IX 3 EOR IX 3 ADC IX 3 ORA 1 1 1 1 IX 3 ADD IX 2 JMP 2 IX 5 JSR IX 3 LDX IX 4 STX 2 MSB LSB IX MSB LSB Bit Manipulation Control IX INH INH IX1 E 9 A B C D IX2 8 EXT 7 DIR REL DIR INH INH 5 6 4 3 2 IX1 Read-Modify-Write DIR DIR MSB LSB 2 2 2 10 SWI INH 2 2 2 2 1 1 1 0 1 Instruction Set 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 9 RTI INH 6 RTS INH General Release Specification 2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2 6 BSR REL 2 2 LDX 2 IMM 2 2 STOP INH 2 2 TXA WAIT INH 1 INH 3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3 4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3 5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2 4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1 2 3 4 5 6 7 8 9 A B Freescale Semiconductor, Inc. Instruction Set For More Information On This Product, Go to: www.freescale.com 0 LSB of Opcode in Hexadecimal REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset C D E F 5 5 3 5 3 3 6 5 BRSET0 BRA BSET0 NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BRN BCLR0 3 1 DIR 2 DIR 2 REL 5 11 5 3 BRSET1 MUL BHI BSET1 3 1 DIR 2 INH DIR 2 REL 5 5 3 5 3 3 6 5 BRCLR1 BLS BCLR1 COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BCC BSET2 LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BNE BSET3 ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BEQ BCLR3 ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BHCC BSET4 ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BHCS BCLR4 ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BPL BSET5 DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BMI BCLR5 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BMC BSET6 INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BMS BCLR6 TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BIL BSET7 3 1 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRCLR7 BIH BCLR7 CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 MSB of Opcode in Hexadecimal MC68HC05CT4 -- Rev. 2.0 INH = Inherent IMM = Immediate DIR = Direct EXT = Extended 0 5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 16. Electrical Specifications 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .128 3.3 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .129 3.3 V and 5.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . .130 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Freescale Semiconductor, Inc... 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 16.11 PLL Signal Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 16.2 Introduction This section contains the electrical and timing specifications. MC68HC05CT4 -- Rev. 2.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 16.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS (VIN or VOUT) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD. Rating Supply Voltage Input Voltage Self-Check Mode (IRQ Pin Only) Current Drain Per Pin Excluding VDD and VSS Operating Junction Temperature Storage Temperature Range Symbol VDD VIN VIN I TJ Tstg Value -0.3 to +7.0 VSS -0.3 to VDD + 0.3 VSS -0.3 to 2 x VDD + 0.3 25 +150 -65 to +150 mA C C Unit V V NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 16.6 5.0 V DC Electrical Characteristics and 16.7 3.3 V DC Electrical Characteristics for guaranteed operating conditions. General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Electrical Specifications Operating Range 16.4 Operating Range Characteristic Operating Temperature Range MC68HC05CT4 (Standard) Symbol TA Value TL to TH 0 to +70 Unit C 16.5 Thermal Characteristics Freescale Semiconductor, Inc... Characteristic Thermal Resistance Plastic Dual In-Line Package Symbol JA Value 70 Unit C/W MC68HC05CT4 -- Rev. 2.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 16.6 5.0 V DC Electrical Characteristics Characteristic Output Voltage ILoad = 10.0 A ILoad = -10.0 A Output High Voltage (ILoad --0.8 mA) Port A, Port B, Port C, Port D Output Low Voltage (ILoad = 1.6 mA) Port A, Port B, Port C, Port D Input High Voltage Port A, Port B, Port C, Port D, IRQ, RE3.5SET, OSC1 Input Low Voltage Port A, Port B, Port C, Port D, IRQ, RESET, OSC1 Input Hysteresis TCAP, RESET, IRQ, PD4/SCK Supply Current (see Notes) Run Wait Stop 25 C 0 C to +70 C Supply Current (see Notes) Run Wait Stop 25 C 0 C to +70 C I/O Ports Hi-Z Leakage Current Port A, Port B, Port D Input Current RESET, IRQ, OSC1 PC0-PC7 with Pullups Enabled Capacitance Ports (as Input or Output) RESET, IRQ Symbol VOL VOH VOH VOL VIH VIL VHYST Min -- VDD -0.1 VDD -0.8 -- 0.7 x VDD VSS 0.8 Typ -- -- -- -- -- -- 0.9 Max 0.1 -- -- 0.4 VDD 0.3 x VDD 1 Unit V V V V V V Freescale Semiconductor, Inc... AGREEMENT IDD -- -- -- -- -- -- -- -- 3 0.3 10 20 1.5 0.5 200 250 -- 10 1 25 30 3 1.3 300 350 5 mA mA A A mA mA A A A A NON-DISCLOSURE IDD2 IOZ IIN -- -- -20 -- -- -- -125 -- -- 10 -250 12 8 COUT CINT pF NOTES: 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 C only 4. Wait IDD and IDD2 : Only timer system active. 5. Run (operating) IDD, IDD2, Wait IDD, and IDD2: Measured using external square wave clock source (fOSC = 10.24 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 6. Wait, stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD -0.2 V 7. Stop IDD and IDD2 are measured with OSC1 = VSS. 8. Wait IDD and IDD2 are affected linearly by the OSC2 capacitance. 9. Run, wait, and stop IDD2 are measured directly off the VDD2 power supply. General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Electrical Specifications 3.3 V DC Electrical Characteristics 16.7 3.3 V DC Electrical Characteristics Characteristic Output Voltage ILoad = 10.0 A ILoad = -10.0 A Output High Voltage (ILoad -0.2 mA) Port A, Port B, Port C, Port D Output Low Voltage (ILoad = 1.6 mA) Port A, Port B, Port C, Port D Symbol VOL VOH VOH VOL VIH VIL Min -- VDD -0.1 VDD -0.3 -- 0.7 x VDD VSS Typ -- -- -- -- -- -- Max 0.1 -- -- 0.3 VDD 0.3 x VDD Unit V V V V V Freescale Semiconductor, Inc... Input High Voltage Port A, Port B, Port C, Port D, IRQ, RESET, OSC1 Input Low Voltage Port A, Port B, Port C, Port D, IRQ, RESET, OSC1 Supply Current (see Notes) Run Wait Stop 25 C 0 C to +70 C Supply Current (see Notes) Run Wait Stop 25 C 0 C to +70 C I/O Ports Hi-Z Leakage Current Port A, Port B, Port D Input Current RESET, IRQ, OSC1 PC0-PC7 with Pullups Enabled Capacitance Ports (as Input or Output) RESET, IRQ IDD -- -- -- -- -- -- -- -- 1.5 0.15 5 10 0.5 0.3 100 125 -- 5 0.5 12 15 2 0.8 150 175 5 mA mA A A mA mA A A A A IDD2 IOZ -- IIN -- -20 -- -- -- -50 -- -- 10 -125 12 8 COUT CINT pF NOTES: 1. VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 C only 4. Wait IDD and IDD2 : Only timer system active. 5. Run (operating) IDD, IDD2, Wait IDD, and IDD2: Measured using external square wave clock source (fOSC = 10.24 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 6. Wait, stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD -0.2 V 7. Stop IDD and IDD2 are measured with OSC1 = VSS. 8. Wait IDD and IDD2 are affected linearly by the OSC2 capacitance. 9. Run, wait, and stop IDD2 are measured directly off the VDD2 power supply. MC68HC05CT4 -- Rev. 2.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 16.8 3.3 V and 5.0 V Control Timing Characteristic Frequency of Operation Crystal External Clock Internal Operating Frequency Crystal (fOSC /5) External Clock (fOSC /5) Cycle Time Symbol fOSC Min -- dc -- dc 488 -- -- 1.5 125 (Note 2) 90 Max 10.24 10.24 2.048 2.048 -- 100 100 -- -- -- -- Unit MHz fOP tCYC tOXOV tILCH tRL tILIH tILIL tOH,tOL MHz ns ms ms tCYC ns tCYC ns Freescale Semiconductor, Inc... AGREEMENT Crystal Oscillator Startup Time Stop Recovery Startup Time (Crystal Oscillator) RESET Pulse Width Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width NOTES: 1. VDD = 3.0 to 5.5 Vdc, VSS = 0 Vdc, TA = 0 oC to +70 oC, unless otherwise noted 2. The minimum period tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 2T tcyc. NON-DISCLOSURE General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Electrical Specifications Comparators 16.9 Comparators Characteristic Input Voltage Range (see Note 2) Voltage Comparator Propagation Time Measured at 100 mV Overdrive (see Note 3) Common Mode Range (see Note 4) Offset (see Note 5) Symbol VINT tCOMP VCOM VOFF tCEN IIN IIN Min VSS -0.5 -- VSS +1.5 -- -- -- -- -- SR VSAT VREF 5 -- x 90% Max VDD +0.5 10 VDD -0.5 20 100 1 4.0 10 -- 0.5 x 110% Unit V s V mV ms A mA kHz V/s V (2/3) VDD Freescale Semiconductor, Inc... Comparator Enable Time (see Note 6) Input Current VSS VIN VDD Input Current VIN VSS Gain Bandwidth Product Slew Rate Saturation Voltage (IOUT = -5 mA) Internal Voltage Reference CMP- NOTES: 1. VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted 2. The comparator is guaranteed to function over the specified input voltage range with no erroneous outputs. 3. Signal propagation time through the comparators measured with 100 mv of overdrive. 4. Comparator is guaranteed to meet specifications; for example, SR, tCOMP, and VOFF. 5. Input offset voltage is guaranteed over the temperature range. 6. Enable time is the time from enabling the comparator with the CEN bit until the comparator is fully functional. 16.10 PWM Timing Characteristic PWM Rise Time PWM Fall Time Symbol tPWMR tPWMR Min 15 15 Max 35 35 Unit ns ns 16.11 PLL Signal Input Characteristic Input Voltage on FINTX and FINRX (peak-to-peak) Input Frequency on FINTX and FINRX Symbol VVCO fVCO Min 200 -- Max -- 60 Unit mVp-p MHz MC68HC05CT4 -- Rev. 2.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Electrical Specifications REQUIRED OSC11 tRL RESET tILIH IRQ2 tILCH IRQ3 4064 tCYC Freescale Semiconductor, Inc... AGREEMENT INTERNAL CLOCK INTERNAL ADDRESS BUS 1FFE 1FFE 1FFE 1FFE 1FFF4 NOTES: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level- and edge-sensitive mask option 4. RESET vector address shown for timing example RESET OR INTERRUPT VECTOR FETCH NON-DISCLOSURE Figure 16-1. Stop Recovery Timing Diagram General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 17. Mechanical Specifications 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 44-Lead Plastic-Leaded Chip Carrier (Case 777-02) . . . . . . .134 44-Lead Quad Flat Pack (Case 824A-01) . . . . . . . . . . . . . . .135 Freescale Semiconductor, Inc... 17.3 17.4 17.2 Introduction The MC68HC05CT4 is available in a 44-pin plastic-leaded chip carrier (PLCC) and a 44-pin quad flat pack (QFP). Package dimensions are provided in this section. The following figures show the latest package information at the time of this publication. To make sure that you have the latest package specifications, contact one of the following: * * Local Motorola Sales Office Motorola Fax Back System (MfaxTM) - Phone 1-602-244-6609 - EMAIL RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/ Worldwide Web (wwweb) home page at http://motorola.com/sps/ * Follow Mfax or wwweb on-line instructions to retrieve the current mechanical specifications. MC68HC05CT4 -- Rev. 2.0 Mechanical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Mechanical Specifications REQUIRED 17.3 44-Lead Plastic-Leaded Chip Carrier (Case 777-02) B 0.007(0.180) M T U L-M S NS NS -N- Y BRK D 0.007(0.180) M T L-M S Z -L-M- Freescale Semiconductor, Inc... AGREEMENT V 44 1 W D X VIEW D-D G1 0.010 (0.25) S T L-M S NS A R Z 0.007(0.180) M T 0.007(0.180) M T L-M S L-M S NS NS H 0.007(0.180) M T L-M S NS J E C G -TG1 0.010 (0.25) S T L-M S NS VIEW S VIEW S NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOLDERS EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSION R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF THE MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMINSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTUSION(S) SHALL NOT CAUSE THE H DIMINSION TO BE GREATER THAN 0.037 (0.940136). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMINISION TO SMALLER THAN 0.025 (0.635). K1 0.004 (0.10) SEATING PLANE K NON-DISCLOSURE F 0.007(0.180) M T L-M S NS INCHES DIM A B C E F G H J K R U V W X Y Z G1 K1 MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.610 0.630 0.040 MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 0.50 2 10 15.50 16.00 1.02 General Release Specification Mechanical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Mechanical Specifications 44-Lead Quad Flat Pack (Case 824A-01) 17.4 44-Lead Quad Flat Pack (Case 824A-01) L 33 34 23 22 S S D D B -A,B,DB 0.20 (0.008) M C A-B 0.05 (0.002) A-B -A- -BB Freescale Semiconductor, Inc... DETAIL A 44 1 11 12 DETAIL A F -DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B S 0.20 (0.008) M H A-B BASE METAL S D S J S N D D S M SECTION B-B CE -CSEATING PLANE -HH DATUM PLANE 0.01 (0.004) G M M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A , B AND D TO BE DETERMINED AT DATUM PLANE H . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE C . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N Q R S T U V W X MILLIMETERS MIN MAX 9.90 10.10 9.90 10.10 2.45 2.10 0.45 0.30 2.10 2.00 0.40 0.30 0.80 BSC 0.25 0.23 0.13 0.95 0.65 8.00 REF 10 5 0.17 0.13 7 0 0.30 0.13 12.95 13.45 0.13 0 12.95 13.45 0.40 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.012 0.018 0.079 0.083 0.012 0.016 0.031 BSC 0.010 0.005 0.009 0.026 0.037 0.315 REF 10 5 0.005 0.007 7 0 0.005 0.012 0.510 0.530 0.005 0 0.510 0.530 0.016 0.063 REF T DATUM PLANE -H- R K W X DETAIL C Q MC68HC05CT4 -- Rev. 2.0 Mechanical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE DETAIL C 0.20 (0.008) M C A-B S D S AGREEMENT L V 0.20 (0.008) M H A-B S REQUIRED S Freescale Semiconductor, Inc. Mechanical Specifications REQUIRED NON-DISCLOSURE General Release Specification Mechanical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05CT4 Section 18. Ordering Information 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .138 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .139 ROM Verification Units (RVUs) . . . . . . . . . . . . . . . . . . . . . . .140 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Freescale Semiconductor, Inc... 18.3 18.4 18.5 18.6 18.7 18.2 Introduction This section contains instructions for ordering custom-masked ROM MCUs. 18.3 MCU Ordering Forms To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Motorola representative. Submit the following items when ordering MCUs: * * * A current MCU ordering form that is completely filled out (Contact your Motorola sales office for assistance.) A copy of the customer specification if the customer specification deviates from the Motorola specification for the MCU Customer's application program on one of the media listed in 18.4 Application Program Media MC68HC05CT4 -- Rev. 2.0 Ordering Information For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Ordering Information REQUIRED The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After making the connection, type bbs in lower-case letters. Then press the return key to start the BBS software. 18.4 Application Program Media Please deliver the application program to Motorola in one of the following media: * * * Macintosh(R)1 3 1/2 inch diskette (double-sided 800 K or double-sided high-density 1.4 M) MS-DOS(R)2 or PC-DOSTM3 3 1/2 inch diskette (double-sided 720 K or double-sided high-density 1.44 M) MS-DOS(R) or PC-DOSTM 5 1/4 inch diskette (double-sided double- density 360K or double-sided high-density 1.2M) Freescale Semiconductor, Inc... AGREEMENT Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with this information: * * * * * * * Customer name Customer part number Project or product name File name of object code Date Name of operating system that formatted diskette Formatted capacity of diskette NON-DISCLOSURE On diskettes, the application program must be in Motorola's S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. 1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. General Release Specification Ordering Information For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Ordering Information ROM Program Verification NOTE: Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all nonuser ROM locations or leave all nonuser ROM locations blank. Refer to the current MCU ordering form for additional requirements. Motorola may request pattern re-submission if nonuser areas contain any nonzero code. If the memory map has two user ROM areas with the same address, then write the two areas in separate files on the diskette. Label the diskette with both file names. Freescale Semiconductor, Inc... In addition to the object code, a file containing the source code can be included. Motorola keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the file name of the source code. 18.5 ROM Program Verification The primary use for the on-chip ROM is to hold the customer's application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. Motorola inputs the customer's application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain nonuser ROM code, such as self-check code. Motorola sends the customer a computer printout of the listing verify file along with a listing verify form. To aid the customer in checking the listing verify file, Motorola will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. Check the listing verify file thoroughly, then complete and sign the listing verify form and return it to Motorola. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask. MC68HC05CT4 -- Rev. 2.0 Ordering Information For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Ordering Information REQUIRED 18.6 ROM Verification Units (RVUs) After receiving the signed listing verify form, Motorola manufactures a custom photographic mask. The mask contains the customer's application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Motorola then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer's user ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Motorola Quality Assurance. Freescale Semiconductor, Inc... AGREEMENT 18.7 MC Order Numbers Table 18-1 shows the MC order numbers for the available package types. Table 18-1. MC Order Numbers MC Order Number MC68HC05CT4FN MC68HC05CT4FB NOTE: FN = 44-Lead Plastic-Leaded Chip Carrier FB = 44-Lead Quad Flat Pack NON-DISCLOSURE Operating Temperature Range 0 C to 70 C 0 C to 70 C General Release Specification Ordering Information For More Information On This Product, Go to: www.freescale.com MC68HC05CT4 -- Rev. 2.0 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064, Japan 0120 191014 +81 2666 8080 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Freescale Semiconductor, Inc... Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. 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